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Date: Tue, 16 Aug 2016 14:21:03 +0100
From: Will Deacon <will.deacon@arm.com>
To: Guenter Roeck <groeck@google.com>
Cc: Robin Murphy <robin.murphy@arm.com>, Kees Cook <keescook@chromium.org>,
        Jeffy Chen <jeffy.chen@rock-chips.com>,
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        Douglas Anderson <dianders@chromium.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        linux-arm-kernel@lists.infradead.org
Subject: Re: Problem with atomic accesses in pstore on some ARM CPUs
Message-ID: <20160816132103.GD27088@arm.com>
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On Tue, Aug 16, 2016 at 06:14:53AM -0700, Guenter Roeck wrote:
> On Tue, Aug 16, 2016 at 3:32 AM, Robin Murphy <robin.murphy@arm.com> wrote:
> > On 16/08/16 00:19, Guenter Roeck wrote:
> >> we are having a problem with atomic accesses in pstore on some ARM
> >> CPUs (specifically rk3288 and rk3399). With those chips, atomic
> >> accesses fail with both pgprot_noncached and pgprot_writecombine
> >> memory. Atomic accesses do work when selecting PAGE_KERNEL protection.
> >
> > What's the pstore backed by? I'm guessing it's not normal DRAM.
> >
> 
> it is normal DRAM.

In which case, why does it need to be mapped with weird attributes?
Is there an alias in the linear map you can use?

Will