From: Peter Zijlstra <peterz@infradead.org>
To: Borislav Petkov <bp@alien8.de>
Cc: Matt Fleming <matt@codeblueprint.co.uk>,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@kernel.org>
Subject: Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2
Date: Fri, 19 Aug 2016 15:34:22 +0200 [thread overview]
Message-ID: <20160819133422.GI10121@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20160818162522.GB5049@nazgul.tnic>
On Thu, Aug 18, 2016 at 06:25:22PM +0200, Borislav Petkov wrote:
> > > I could try to find better/more fitting event selectors on AMD...
> >
> > If you've got any other suggestions, I'm all ears.
>
> So there are no LLC events on AMD in the sense that there are no
> event selectors which always mean last-level cache and select those
> automagically, no matter whether the LLC is the L2, L3 and so on,
> depending on the part.
>
> If we have to be correct on AMD, we'd have to check whether the part has
> an L3 and then choose the L3 events, say, something like
>
> "EventSelect 4E1h L3 Cache Misses" and "EventSelect 4E2h L3 Fills caused
> by L2 Evictions"
Can't those events are NB events and cannot be used on per CPU counters.
The 7D,7E L2 events are the best that are available on AMD afaict.
next prev parent reply other threads:[~2016-08-19 13:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-11 15:21 [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Matt Fleming
2016-08-11 16:41 ` Borislav Petkov
2016-08-15 15:13 ` Matt Fleming
2016-08-18 16:25 ` Borislav Petkov
2016-08-19 13:34 ` Peter Zijlstra [this message]
2016-08-19 14:44 ` Borislav Petkov
2016-08-19 15:16 ` Peter Zijlstra
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