From: Peter Zijlstra <peterz@infradead.org>
To: Borislav Petkov <bp@alien8.de>
Cc: Matt Fleming <matt@codeblueprint.co.uk>,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@kernel.org>
Subject: Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2
Date: Fri, 19 Aug 2016 17:16:42 +0200 [thread overview]
Message-ID: <20160819151642.GF10153@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20160819144453.GA8459@nazgul.tnic>
On Fri, Aug 19, 2016 at 04:44:53PM +0200, Borislav Petkov wrote:
> On Fri, Aug 19, 2016 at 03:34:22PM +0200, Peter Zijlstra wrote:
> > Can't those events are NB events and cannot be used on per CPU counters.
>
> It fugures, considering L3 is part of the NB on AMD.
>
> So the Intel ones are special in the sense that they can be used on per
> CPU counters even though they're not really per-CPU?
Intel has L3 (and L2,1) request and miss events per logical CPU. The CPU
still issues the load/store that causes the request and miss and thus
can be accounted to the program under execution.
Intel also has a bunch of L3 events at the uncore of course.
prev parent reply other threads:[~2016-08-19 15:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-11 15:21 [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Matt Fleming
2016-08-11 16:41 ` Borislav Petkov
2016-08-15 15:13 ` Matt Fleming
2016-08-18 16:25 ` Borislav Petkov
2016-08-19 13:34 ` Peter Zijlstra
2016-08-19 14:44 ` Borislav Petkov
2016-08-19 15:16 ` Peter Zijlstra [this message]
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