From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755556AbcHSPQt (ORCPT ); Fri, 19 Aug 2016 11:16:49 -0400 Received: from merlin.infradead.org ([205.233.59.134]:36436 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755536AbcHSPQr (ORCPT ); Fri, 19 Aug 2016 11:16:47 -0400 Date: Fri, 19 Aug 2016 17:16:42 +0200 From: Peter Zijlstra To: Borislav Petkov Cc: Matt Fleming , linux-kernel@vger.kernel.org, Ingo Molnar Subject: Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Message-ID: <20160819151642.GF10153@twins.programming.kicks-ass.net> References: <1470928902-31196-1-git-send-email-matt@codeblueprint.co.uk> <20160811164150.GB7296@nazgul.tnic> <20160815151316.GI30909@codeblueprint.co.uk> <20160818162522.GB5049@nazgul.tnic> <20160819133422.GI10121@twins.programming.kicks-ass.net> <20160819144453.GA8459@nazgul.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160819144453.GA8459@nazgul.tnic> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 19, 2016 at 04:44:53PM +0200, Borislav Petkov wrote: > On Fri, Aug 19, 2016 at 03:34:22PM +0200, Peter Zijlstra wrote: > > Can't those events are NB events and cannot be used on per CPU counters. > > It fugures, considering L3 is part of the NB on AMD. > > So the Intel ones are special in the sense that they can be used on per > CPU counters even though they're not really per-CPU? Intel has L3 (and L2,1) request and miss events per logical CPU. The CPU still issues the load/store that causes the request and miss and thus can be accounted to the program under execution. Intel also has a bunch of L3 events at the uncore of course.