From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755990AbcHXS2D (ORCPT ); Wed, 24 Aug 2016 14:28:03 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:40351 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754189AbcHXS2B (ORCPT ); Wed, 24 Aug 2016 14:28:01 -0400 Date: Wed, 24 Aug 2016 20:27:06 +0200 From: Peter Zijlstra To: Borislav Petkov Cc: Matt Fleming , linux-kernel@vger.kernel.org, Ingo Molnar , stable@vger.kernel.org Subject: Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Message-ID: <20160824182706.GD10153@twins.programming.kicks-ass.net> References: <1472044328-21302-1-git-send-email-matt@codeblueprint.co.uk> <20160824145514.GA29210@nazgul.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160824145514.GA29210@nazgul.tnic> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 24, 2016 at 04:55:14PM +0200, Borislav Petkov wrote: > On Wed, Aug 24, 2016 at 02:12:08PM +0100, Matt Fleming wrote: > > While the Intel PMU monitors the LLC when perf enables the > > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > > L1 instruction cache fetches (0x0080) and instruction cache misses > > (0x0081) on the AMD PMU. > > > > This is extremely confusing when monitoring the same workload across > > Intel and AMD machines, since parameters like, > > > > $ perf stat -e cache-references,cache-misses > > > > measure completely different things. > > > > Instead, make the AMD PMU measure instruction/data cache and TLB fill > > requests to the L2 and instruction/data cache and TLB misses in the L2 > > when HW_CACHE_REFERENCES and HW_CACHE_MISSES are enabled, > > respectively. That way the events measure unified caches on both > > platforms. > > I'm still not really sure about this: we can't really compare L3 to L2 > access patterns - it is almost as comparing apples to oranges. Can we > use the Intel L2 events instead? They're not meant to be comparable between machines. I wouldn't even compare the LLC numbers between two different Intel parts. These events are meant to profile a workload on the machine you run them on. Big cache-miss/ref ratios indicate you loose performance because of the memory subsystem and or data structure layout. And afaict AMD parts, even those that have L3, cannot provide L3 numbers on a per task basis, so these L2 numbers are the best we have.