From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760420AbcHYQn5 (ORCPT ); Thu, 25 Aug 2016 12:43:57 -0400 Received: from mga14.intel.com ([192.55.52.115]:35240 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759548AbcHYQnx (ORCPT ); Thu, 25 Aug 2016 12:43:53 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,576,1464678000"; d="scan'208";a="1041459021" Date: Thu, 25 Aug 2016 09:43:51 -0700 From: Bin Gao To: Thomas Gleixner Cc: Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, bin.gao@intel.com Subject: Re: [PATCH v2] x86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined calibration Message-ID: <20160825164350.GA245186@worksta> References: <20160816174240.GA33372@worksta> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 24, 2016 at 10:51:20AM +0200, Thomas Gleixner wrote: > On Tue, 16 Aug 2016, Bin Gao wrote: > > On some newer Intel x86 processors/SoCs the TSC frequency can be directly > > calculated by factors read from specific MSR registers or from a cpuid > > leaf (0x15). TSC frequency calculated by native msr/cpuid is absolutely > > accurate so we should always skip calibrating TSC aginst another clock, > > e.g. PIT, HPET, etc. So we want to skip the refined calibration by setting > > the X86_FEATURE_TSC_RELIABLE flag. Existing code setting the flag by > > set_cpu_cap() doesn't work as the flag is cleared later in identify_cpu(). > > A cpu caps flag is not cleared only if it's set by setup_force_cpu_cap(). > > This patch converted set_cpu_cap() to setup_force_cpu_cap() to ensure > > refined calibration is skipped. > > > > We had a test on Intel CherryTrail platform: the 24 hours time drift is > > 3.6 seconds if refined calibration was not skipped while the drift is less > > than 0.6 second when refined calibration was skipped. > > > > Correctly setting the X86_FEATURE_TSC_RELIABLE flag also guarantees TSC is > > not monitored by timekeeping watchdog because on most of these system TSC > > is the only reliable clocksource. HPET, for instance, works but may not > > be reliable. So kernel may report a physically reliable TSC is not reliable > > just because a physically not reliable HPET is acting as timekeeping > > watchdog. > > What about non SoC systems where the MSR is available, but we still see that > cross socket TSC wreckage? This change will prevent the watchdog from > detecting that. MSR is only available on Intel Atom SoCs. There is no such a multi-socket system. > > Thanks, > > tglx