From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753900AbcHZU7h (ORCPT ); Fri, 26 Aug 2016 16:59:37 -0400 Received: from down.free-electrons.com ([37.187.137.238]:54777 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751014AbcHZU7f (ORCPT ); Fri, 26 Aug 2016 16:59:35 -0400 Date: Fri, 26 Aug 2016 22:49:14 +0200 From: Maxime Ripard To: LABBE Corentin Cc: robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, davem@davemloft.net, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2 1/5] ethernet: add sun8i-emac driver Message-ID: <20160826204914.GD3165@lukather> References: <1469001800-11615-1-git-send-email-clabbe.montjoie@gmail.com> <1469001800-11615-2-git-send-email-clabbe.montjoie@gmail.com> <20160725195455.GQ7419@lukather> <20160824120221.GB29212@Red> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="BI5RvnYi6R4T2M87" Content-Disposition: inline In-Reply-To: <20160824120221.GB29212@Red> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --BI5RvnYi6R4T2M87 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Aug 24, 2016 at 02:02:21PM +0200, LABBE Corentin wrote: > > > +/* Set Management Data Clock, must be call after device reset */ > > > +static void sun8i_emac_set_mdc(struct net_device *ndev) > > > +{ > > > + struct sun8i_emac_priv *priv =3D netdev_priv(ndev); > > > + unsigned long rate; > > > + u32 reg; > > > + > > > + rate =3D clk_get_rate(priv->ahb_clk); > > > + if (rate > 160000000) > > > + reg =3D 0x3 << 20; /* AHB / 128 */ > > > + else if (rate > 80000000) > > > + reg =3D 0x2 << 20; /* AHB / 64 */ > > > + else if (rate > 40000000) > > > + reg =3D 0x1 << 20; /* AHB / 32 */ > > > + else > > > + reg =3D 0x0 << 20; /* AHB / 16 */ > > > + netif_dbg(priv, link, ndev, "MDC auto : %x\n", reg); > > > + writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD); > >=20 > > You could also expose that as a clock. > >=20 >=20 > For which purpose ? > No ethernet driver expose the MDC as clock and I dont see any interest: > - I dont think that tuning it give any gain > - Knowing it's value is of little interest You don't have to implement anything, you can just register a clk_div driver, and everything works, and you would use the proper clock APIs (ie. clk_set_rate, and that's it). That would be exposed just like any other clock, including in debugfs, which would remove the need for the debug call. But this really was just a suggestion. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --BI5RvnYi6R4T2M87 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXwKtKAAoJEBx+YmzsjxAgRT8P/A2F+uwyRd0yzSAwNDdAVXl1 CcYRnJesld1GySGao+kwS8tYydpl8/ouUtMdgG9ZmuiQ5wzAIOYI7uha2hNFkCnE 2+JOC8x6XNL6wLjCkNtDjqwnBVM4wV4HXNA/SSPF4jA7Ckzvb+J/heDa0yNheF7E 9gipKPLiy/wPYoH8StaX/QC1jQCbWxilhm9b0230wwsMzdRe2F46E+PD0CDvjwRH g2hyNj3SeLAGoXQUL9XhUp3Z7ly1YfC08+gT3O9nQGkP46NXbdV82gDcC/FeEwtg YxihZu6097UYJLcWgAtZTZgO67WYDOHdGpeFJ/zxpnXPGFQ/JTDADbe3WClYk6qq kP3PkA14SUgvEiBSas8KhoY2nwj9by3p8ZllqfrLlQRtfAyWp79DSgFcvVpHZKz9 +tP0YNEaid9a7LwDpeCOnvY2ADVPG7F8RnndIxWChPAUobxz4jgrSz6srqywptQF ZudqvS/AT2LcEWFOnIbYwk3ReOqofUPRgOrK4DUPmg4Mk3tz2LHBFPJrLbJcbqCh doDSctCMYytwDFgNyvl3Ps9Ei08TQmUnxmTX1QPzA6XcHxrVeU+pGHBNB0pEFaZ2 vP6J2ebIG9zhXN+sRQ0OpvzLGVhZTXeacjQpr9ob5OD5PK1/rul4HaRX0RDBm5ep 6Ea9+8iMTdPSrMD/4T5q =3/yB -----END PGP SIGNATURE----- --BI5RvnYi6R4T2M87--