From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756831AbcILH7v (ORCPT ); Mon, 12 Sep 2016 03:59:51 -0400 Received: from mail.skyhub.de ([78.46.96.112]:55363 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753142AbcILH7q (ORCPT ); Mon, 12 Sep 2016 03:59:46 -0400 From: Borislav Petkov To: X86 ML Cc: LKML Subject: [PATCH 01/15] x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks() Date: Mon, 12 Sep 2016 09:59:27 +0200 Message-Id: <20160912075941.24699-2-bp@alien8.de> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20160912075941.24699-1-bp@alien8.de> References: <20160912075941.24699-1-bp@alien8.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Change MSR_IA32_MCx_MISC() macro to msr_ops.misc() because SMCA machines define a different set of MSRs and msr_ops will give you the correct MISC register. Signed-off-by: Yazen Ghannam Cc: Aravind Gopalakrishnan Cc: Tony Luck Cc: linux-edac Cc: x86-ml Link: http://lkml.kernel.org/r/1468269447-8808-1-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Borislav Petkov --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 7b7f3be783d4..78b7681f7f66 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -869,7 +869,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank) } } - err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); + err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); if (!err) goto out; -- 2.10.0