From: Borislav Petkov <bp@alien8.de>
To: X86 ML <x86@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 07/15] EDAC/mce_amd: Use SMCA prefix for error descriptions arrays
Date: Mon, 12 Sep 2016 09:59:33 +0200 [thread overview]
Message-ID: <20160912075941.24699-8-bp@alien8.de> (raw)
In-Reply-To: <20160912075941.24699-1-bp@alien8.de>
From: Yazen Ghannam <Yazen.Ghannam@amd.com>
The error descriptions defined for Fam17h can be reused for other SMCA
systems, so their names should reflect this.
Change f17h prefix to smca for error descriptions.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1472673994-12235-4-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
drivers/edac/mce_amd.c | 80 +++++++++++++++++++++++++-------------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 455cd49d6253..ea549a94361b 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -148,12 +148,12 @@ static const char * const mc6_mce_desc[] = {
};
/* Scalable MCA error strings */
-static const char * const f17h_ls_mce_desc[] = {
+static const char * const smca_ls_mce_desc[] = {
"Load queue parity",
"Store queue parity",
"Miss address buffer payload parity",
"L1 TLB parity",
- "", /* reserved */
+ "Reserved",
"DC tag error type 6",
"DC tag error type 1",
"Internal error type 1",
@@ -172,7 +172,7 @@ static const char * const f17h_ls_mce_desc[] = {
"L2 fill data error",
};
-static const char * const f17h_if_mce_desc[] = {
+static const char * const smca_if_mce_desc[] = {
"microtag probe port parity error",
"IC microtag or full tag multi-hit error",
"IC full tag parity",
@@ -189,14 +189,14 @@ static const char * const f17h_if_mce_desc[] = {
"System Read Data error",
};
-static const char * const f17h_l2_mce_desc[] = {
+static const char * const smca_l2_mce_desc[] = {
"L2M tag multi-way-hit error",
"L2M tag ECC error",
"L2M data ECC error",
"HW assert",
};
-static const char * const f17h_de_mce_desc[] = {
+static const char * const smca_de_mce_desc[] = {
"uop cache tag parity error",
"uop cache data parity error",
"Insn buffer parity error",
@@ -208,7 +208,7 @@ static const char * const f17h_de_mce_desc[] = {
"uop buffer parity"
};
-static const char * const f17h_ex_mce_desc[] = {
+static const char * const smca_ex_mce_desc[] = {
"Watchdog timeout error",
"Phy register file parity",
"Flag register file parity",
@@ -222,7 +222,7 @@ static const char * const f17h_ex_mce_desc[] = {
"Branch buffer queue parity error",
};
-static const char * const f17h_fp_mce_desc[] = {
+static const char * const smca_fp_mce_desc[] = {
"Physical register file parity",
"Freelist parity error",
"Schedule queue parity",
@@ -232,7 +232,7 @@ static const char * const f17h_fp_mce_desc[] = {
"Hardware assertion",
};
-static const char * const f17h_l3_mce_desc[] = {
+static const char * const smca_l3_mce_desc[] = {
"Shadow tag macro ECC error",
"Shadow tag macro multi-way-hit error",
"L3M tag ECC error",
@@ -243,7 +243,7 @@ static const char * const f17h_l3_mce_desc[] = {
"L3 HW assert",
};
-static const char * const f17h_cs_mce_desc[] = {
+static const char * const smca_cs_mce_desc[] = {
"Illegal request from transport layer",
"Address violation",
"Security violation",
@@ -255,14 +255,14 @@ static const char * const f17h_cs_mce_desc[] = {
"ECC error on probe filter access",
};
-static const char * const f17h_pie_mce_desc[] = {
+static const char * const smca_pie_mce_desc[] = {
"HW assert",
"Internal PIE register security violation",
"Error on GMI link",
"Poison data written to internal PIE register",
};
-static const char * const f17h_umc_mce_desc[] = {
+static const char * const smca_umc_mce_desc[] = {
"DRAM ECC error",
"Data poison error on DRAM",
"SDP parity error",
@@ -271,15 +271,15 @@ static const char * const f17h_umc_mce_desc[] = {
"Write data CRC error",
};
-static const char * const f17h_pb_mce_desc[] = {
+static const char * const smca_pb_mce_desc[] = {
"Parameter Block RAM ECC error",
};
-static const char * const f17h_psp_mce_desc[] = {
+static const char * const smca_psp_mce_desc[] = {
"PSP RAM ECC or parity error",
};
-static const char * const f17h_smu_mce_desc[] = {
+static const char * const smca_smu_mce_desc[] = {
"SMU RAM ECC or parity error",
};
@@ -837,8 +837,8 @@ static void decode_f17h_core_errors(const char *ip_name, u8 xec,
switch (mca_type) {
case SMCA_LS:
- error_desc_array = f17h_ls_mce_desc;
- len = ARRAY_SIZE(f17h_ls_mce_desc) - 1;
+ error_desc_array = smca_ls_mce_desc;
+ len = ARRAY_SIZE(smca_ls_mce_desc) - 1;
if (xec == 0x4) {
pr_cont("Unrecognized LS MCA error code.\n");
@@ -847,33 +847,33 @@ static void decode_f17h_core_errors(const char *ip_name, u8 xec,
break;
case SMCA_IF:
- error_desc_array = f17h_if_mce_desc;
- len = ARRAY_SIZE(f17h_if_mce_desc) - 1;
+ error_desc_array = smca_if_mce_desc;
+ len = ARRAY_SIZE(smca_if_mce_desc) - 1;
break;
case SMCA_L2_CACHE:
- error_desc_array = f17h_l2_mce_desc;
- len = ARRAY_SIZE(f17h_l2_mce_desc) - 1;
+ error_desc_array = smca_l2_mce_desc;
+ len = ARRAY_SIZE(smca_l2_mce_desc) - 1;
break;
case SMCA_DE:
- error_desc_array = f17h_de_mce_desc;
- len = ARRAY_SIZE(f17h_de_mce_desc) - 1;
+ error_desc_array = smca_de_mce_desc;
+ len = ARRAY_SIZE(smca_de_mce_desc) - 1;
break;
case SMCA_EX:
- error_desc_array = f17h_ex_mce_desc;
- len = ARRAY_SIZE(f17h_ex_mce_desc) - 1;
+ error_desc_array = smca_ex_mce_desc;
+ len = ARRAY_SIZE(smca_ex_mce_desc) - 1;
break;
case SMCA_FP:
- error_desc_array = f17h_fp_mce_desc;
- len = ARRAY_SIZE(f17h_fp_mce_desc) - 1;
+ error_desc_array = smca_fp_mce_desc;
+ len = ARRAY_SIZE(smca_fp_mce_desc) - 1;
break;
case SMCA_L3_CACHE:
- error_desc_array = f17h_l3_mce_desc;
- len = ARRAY_SIZE(f17h_l3_mce_desc) - 1;
+ error_desc_array = smca_l3_mce_desc;
+ len = ARRAY_SIZE(smca_l3_mce_desc) - 1;
break;
default:
@@ -899,13 +899,13 @@ static void decode_df_errors(u8 xec, unsigned int mca_type)
switch (mca_type) {
case SMCA_CS:
- error_desc_array = f17h_cs_mce_desc;
- len = ARRAY_SIZE(f17h_cs_mce_desc) - 1;
+ error_desc_array = smca_cs_mce_desc;
+ len = ARRAY_SIZE(smca_cs_mce_desc) - 1;
break;
case SMCA_PIE:
- error_desc_array = f17h_pie_mce_desc;
- len = ARRAY_SIZE(f17h_pie_mce_desc) - 1;
+ error_desc_array = smca_pie_mce_desc;
+ len = ARRAY_SIZE(smca_pie_mce_desc) - 1;
break;
default:
@@ -963,23 +963,23 @@ static void decode_smca_errors(struct mce *m)
break;
case SMCA_UMC:
- error_desc_array = f17h_umc_mce_desc;
- len = ARRAY_SIZE(f17h_umc_mce_desc) - 1;
+ error_desc_array = smca_umc_mce_desc;
+ len = ARRAY_SIZE(smca_umc_mce_desc) - 1;
break;
case SMCA_PB:
- error_desc_array = f17h_pb_mce_desc;
- len = ARRAY_SIZE(f17h_pb_mce_desc) - 1;
+ error_desc_array = smca_pb_mce_desc;
+ len = ARRAY_SIZE(smca_pb_mce_desc) - 1;
break;
case SMCA_PSP:
- error_desc_array = f17h_psp_mce_desc;
- len = ARRAY_SIZE(f17h_psp_mce_desc) - 1;
+ error_desc_array = smca_psp_mce_desc;
+ len = ARRAY_SIZE(smca_psp_mce_desc) - 1;
break;
case SMCA_SMU:
- error_desc_array = f17h_smu_mce_desc;
- len = ARRAY_SIZE(f17h_smu_mce_desc) - 1;
+ error_desc_array = smca_smu_mce_desc;
+ len = ARRAY_SIZE(smca_smu_mce_desc) - 1;
break;
default:
--
2.10.0
next prev parent reply other threads:[~2016-09-12 8:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-12 7:59 [PATCH 00/15] x86/RAS queue for 4.9 Borislav Petkov
2016-09-12 7:59 ` [PATCH 01/15] x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks() Borislav Petkov
2016-09-12 7:59 ` [PATCH 02/15] x86/mce: Add support for new MCA_SYND register Borislav Petkov
2016-09-12 7:59 ` [PATCH 03/15] EDAC/mce_amd: Print syndrome register value on SMCA systems Borislav Petkov
2016-09-12 7:59 ` [PATCH 04/15] x86/RAS: Add syndrome support to mce_amd_inj Borislav Petkov
2016-09-12 7:59 ` [PATCH 05/15] x86/mce/AMD: Read MSRs on the CPU allocating the threshold blocks Borislav Petkov
2016-09-12 7:59 ` [PATCH 06/15] EDAC/mce_amd: Add missing SMCA error descriptions Borislav Petkov
2016-09-12 7:59 ` Borislav Petkov [this message]
2016-09-12 7:59 ` [PATCH 08/15] x86/mce/AMD, EDAC/mce_amd: Define and use tables for known SMCA IP types Borislav Petkov
2016-09-12 7:59 ` [PATCH 09/15] x86/mce/AMD: Update sysfs bank names for SMCA systems Borislav Petkov
2016-09-12 7:59 ` [PATCH 10/15] x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on " Borislav Petkov
2016-09-12 7:59 ` [PATCH 11/15] x86/mce/AMD: Save MCA_IPID in MCE struct " Borislav Petkov
2016-09-12 7:59 ` [PATCH 12/15] x86/mce, EDAC/mce_amd: Print MCA_SYND and MCA_IPID during MCE " Borislav Petkov
2016-09-12 7:59 ` [PATCH 13/15] x86/mce/AMD: Extract the error address " Borislav Petkov
2016-09-12 7:59 ` [PATCH 14/15] x86/MCE/AMD, EDAC: Handle reserved bank 4 on Fam17h properly Borislav Petkov
2016-09-12 7:59 ` [PATCH 15/15] x86/RAS/mce_amd_inj: Fix some W= warnings Borislav Petkov
2016-09-13 13:33 ` [tip:ras/core] " tip-bot for Borislav Petkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160912075941.24699-8-bp@alien8.de \
--to=bp@alien8.de \
--cc=linux-kernel@vger.kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox