From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765173AbcIOAWU (ORCPT ); Wed, 14 Sep 2016 20:22:20 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:46984 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756264AbcIOAWR (ORCPT ); Wed, 14 Sep 2016 20:22:17 -0400 Date: Thu, 15 Sep 2016 02:22:08 +0200 From: Andrew Lunn To: John Crispin Cc: "David S. Miller" , Florian Fainelli , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, qsdk-review@qca.qualcomm.com, devicetree@vger.kernel.org Subject: Re: [PATCH V2 1/3] Documentation: devicetree: add qca8k binding Message-ID: <20160915002208.GA29110@lunn.ch> References: <1473849542-3298-1-git-send-email-john@phrozen.org> <1473849542-3298-2-git-send-email-john@phrozen.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1473849542-3298-2-git-send-email-john@phrozen.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 14, 2016 at 12:39:00PM +0200, John Crispin wrote: > Add device-tree binding for ar8xxx switch families. > > Cc: devicetree@vger.kernel.org > Signed-off-by: John Crispin > --- > Changes in V2 > * fixup ecample to include phy nodes and corresponding phandles > * add a note explaining why we need to phy nodes > > .../devicetree/bindings/net/dsa/qca8k.txt | 88 ++++++++++++++++++++ > 1 file changed, 88 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt > > diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt > new file mode 100644 > index 0000000..2c1582a > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt > @@ -0,0 +1,88 @@ > +* Qualcomm Atheros QCA8xxx switch family > + > +Required properties: > + > +- compatible: should be "qca,qca8337" > +- #size-cells: must be 0 > +- #address-cells: must be 1 > + > +Subnodes: > + > +The integrated switch subnode should be specified according to the binding > +described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of > +port and PHY id, each subnode describing a port needs to have a valid phandle > +referencing the internal PHY connected to it. Hi John I've not looked at the driver yet, but you said yesterday the CPU port has to be port 0. I think it would be good to document that here. Otherwise, this is looking good. Andrew