From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757548AbcIUOen (ORCPT ); Wed, 21 Sep 2016 10:34:43 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:36888 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757448AbcIUOel (ORCPT ); Wed, 21 Sep 2016 10:34:41 -0400 Date: Wed, 21 Sep 2016 16:34:37 +0200 From: Daniel Lezcano To: Meng Yi Cc: tglx@linutronix.de, alexander.stein@systec-electronic.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] clocksource/fsl: Fix errata A-007728 for flextimer Message-ID: <20160921143437.GA1442@mai> References: <1474181161-1975-1-git-send-email-meng.yi@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1474181161-1975-1-git-send-email-meng.yi@nxp.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Sep 18, 2016 at 02:46:01PM +0800, Meng Yi wrote: > If the FTM counter reaches the FTM_MOD value between the reading of the > TOF bit and the writing of 0 to the TOF bit, the process of clearing the > TOF bit does not work as expected when FTMx_CONF[NUMTOF] != 0 and the > current TOF count is less than FTMx_CONF[NUMTOF]. If the above condition > is met, the TOF bit remains set. If the TOF interrupt is enabled > (FTMx_SC[TOIE] = 1), the TOF interrupt also remains asserted. > > Above is the errata discription > > The workaround is clearing TOF bit until it is cleaned(FTM counter doesn't > always reache the FTM_MOD anyway),which may cost some cycles. > > Signed-off-by: Meng Yi > --- > Change in V2: > -add timeout into IRQ context(suggested by Alexander) > --- > drivers/clocksource/fsl_ftm_timer.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/clocksource/fsl_ftm_timer.c b/drivers/clocksource/fsl_ftm_timer.c > index 738515b..86f9186 100644 > --- a/drivers/clocksource/fsl_ftm_timer.c > +++ b/drivers/clocksource/fsl_ftm_timer.c > @@ -83,11 +83,13 @@ static inline void ftm_counter_disable(void __iomem *base) > > static inline void ftm_irq_acknowledge(void __iomem *base) > { > - u32 val; > + unsigned long timeout = jiffies + msecs_to_jiffies(100); Do you expect the jiffies to be updated when we are in the timer irq handler ? > - val = ftm_readl(base + FTM_SC); > - val &= ~FTM_SC_TOF; > - ftm_writel(val, base + FTM_SC); > + /*read and clean the FTM_SC_TOF bit until its cleared*/ > + while ((FTM_SC_TOF & ftm_readl(base + FTM_SC)) && > + time_before(jiffies, timeout)) > + ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF), > + base + FTM_SC); > } > > static inline void ftm_irq_enable(void __iomem *base) > -- > 2.1.0.27.g96db324 >