linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: "Radim Krčmář" <rkrcmar@redhat.com>
To: Wanpeng Li <kernellwp@gmail.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	Wanpeng Li <wanpeng.li@hotmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Wincy Van <fanwenyi0529@gmail.com>,
	Yang Zhang <yang.zhang.wz@gmail.com>
Subject: Re: [PATCH v3] Enable MSR-BASED TPR shadow even if APICv is inactive
Date: Wed, 21 Sep 2016 18:35:07 +0200	[thread overview]
Message-ID: <20160921163507.GA2097@potion> (raw)
In-Reply-To: <1474424076-6596-1-git-send-email-wanpeng.li@hotmail.com>

2016-09-21 10:14+0800, Wanpeng Li:
> From: Wanpeng Li <wanpeng.li@hotmail.com>
> 
> I observed that kvmvapic(to optimize flexpriority=N or AMD) is used 
> to boost TPR access when testing kvm-unit-test/eventinj.flat tpr case
> on my haswell desktop (w/ flexpriority, w/o APICv). Commit (8d14695f9542 
> x86, apicv: add virtual x2apic support) disable virtual x2apic mode 
> completely if w/o APICv, and the author also told me that windows guest
> can't enter into x2apic mode when he developed the APICv feature several 
> years ago. However, it is not truth currently, Interrupt Remapping and 
> vIOMMU is added to qemu and the developers from Intel test windows 8 can 
> work in x2apic mode w/ Interrupt Remapping enabled recently. 
> 
> This patch enables TPR shadow for virtual x2apic mode to boost 
> windows guest in x2apic mode even if w/o APICv.
> 
> Can pass the kvm-unit-test.
> 
> Suggested-by: Radim Krčmář <rkrcmar@redhat.com>
> Suggested-by: Wincy Van <fanwenyi0529@gmail.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Radim Krčmář <rkrcmar@redhat.com>
> Cc: Wincy Van <fanwenyi0529@gmail.com>
> Cc: Yang Zhang <yang.zhang.wz@gmail.com>
> Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com>
> ---
> v2 -> v3:
>  * introduce a new set of bitmaps and assign them in vmx_set_msr_bitmap()
> v1 -> v2: 
>  * leverage the cached msr bitmap
> 
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> @@ -2518,10 +2520,18 @@ static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
>  	else if (cpu_has_secondary_exec_ctrls() &&
>  		 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
>  		  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
> -		if (is_long_mode(vcpu))
> -			msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
> -		else
> -			msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
> +		if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
> +			if (is_long_mode(vcpu))
> +				msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
> +			else
> +				msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
> +		} else if ((enable_apicv && !kvm_vcpu_apicv_active(vcpu)) ||
> +				!enable_apicv) {

Could only be "else" without if here.  I'll change that when refactoring
of vmx bitmap handling, posting soon (hopefully).

> +			if (is_long_mode(vcpu))
> +				msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv_inactive;
> +			else
> +				msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv_inactive;
> +		}
>  	} else {
>  		if (is_long_mode(vcpu))
>  			msr_bitmap = vmx_msr_bitmap_longmode;
> @@ -4678,28 +4688,49 @@ static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
> -static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
> +static void vmx_enable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)
>  {
> -	__vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
> -			msr, MSR_TYPE_R);
> -	__vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
> -			msr, MSR_TYPE_R);
> +	if (apicv_active) {
> +		__vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
> +				msr, MSR_TYPE_R);
> +		__vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
> +				msr, MSR_TYPE_R);
> +	} else {
> +		__vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv_inactive,
> +				msr, MSR_TYPE_R);
> +		__vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv_inactive,
> +				msr, MSR_TYPE_R);

Pasto here (disable vs. enable).  It's not called with !apicv_active and
the refactoring will delete the whole function, so

Reviwed-by: Radim Krčmář <rkrcmar@redhat.com>

  parent reply	other threads:[~2016-09-21 16:35 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-21  2:14 [PATCH v3] Enable MSR-BASED TPR shadow even if APICv is inactive Wanpeng Li
2016-09-21  2:38 ` Wanpeng Li
2016-09-21 16:35 ` Radim Krčmář [this message]
2016-09-21 23:17   ` Wanpeng Li

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160921163507.GA2097@potion \
    --to=rkrcmar@redhat.com \
    --cc=fanwenyi0529@gmail.com \
    --cc=kernellwp@gmail.com \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=pbonzini@redhat.com \
    --cc=wanpeng.li@hotmail.com \
    --cc=yang.zhang.wz@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).