From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034004AbcIWVqV (ORCPT ); Fri, 23 Sep 2016 17:46:21 -0400 Received: from mail-oi0-f65.google.com ([209.85.218.65]:33911 "EHLO mail-oi0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752839AbcIWVqS (ORCPT ); Fri, 23 Sep 2016 17:46:18 -0400 Date: Fri, 23 Sep 2016 16:46:16 -0500 From: Rob Herring To: Brian Norris Cc: Bjorn Helgaas , linux-kernel@vger.kernel.org, Shawn Lin , devicetree@vger.kernel.org, Jeffy Chen , Wenrui Li , Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH] PCI: rockchip: Support quirk to disable 5 GT/s (PCIe 2.x) link rate Message-ID: <20160923214616.GA30743@rob-hp-laptop> References: <1474565478-27242-1-git-send-email-briannorris@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1474565478-27242-1-git-send-email-briannorris@chromium.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 22, 2016 at 10:31:18AM -0700, Brian Norris wrote: > rk3399 supports PCIe 2.x link speeds marginally at best, and on some > boards, the link won't train at 5 GT/s at all. Rather than sacrifice 500 > ms waiting for training that will never happen, let's support a device > tree quirk flag to disable generation 2 speeds entirely. > > Signed-off-by: Brian Norris > --- > .../devicetree/bindings/pci/rockchip-pcie.txt | 2 + > drivers/pci/host/pcie-rockchip.c | 57 +++++++++++++--------- > 2 files changed, 37 insertions(+), 22 deletions(-) Acked-by: Rob Herring