From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934335AbcI2RXf (ORCPT ); Thu, 29 Sep 2016 13:23:35 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:50475 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933853AbcI2RX1 (ORCPT ); Thu, 29 Sep 2016 13:23:27 -0400 Date: Thu, 29 Sep 2016 10:23:22 -0700 From: "Paul E. McKenney" To: Will Deacon Cc: Peter Zijlstra , linux-kernel@vger.kernel.org, mingo@kernel.org, dhowells@redhat.com, stern@rowland.harvard.edu Subject: Re: [PATCH locking/Documentation 1/2] Add note of release-acquire store vulnerability Reply-To: paulmck@linux.vnet.ibm.com References: <20160929155401.GA5097@linux.vnet.ibm.com> <20160929155817.GB5016@twins.programming.kicks-ass.net> <20160929160307.GT13862@arm.com> <20160929164353.GX14933@linux.vnet.ibm.com> <20160929171036.GV13862@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160929171036.GV13862@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16092917-0020-0000-0000-000009E95C24 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00005826; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000186; SDB=6.00762765; UDB=6.00363599; IPR=6.00537899; BA=6.00004771; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00012821; XFM=3.00000011; UTC=2016-09-29 17:23:24 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16092917-0021-0000-0000-00005609340F Message-Id: <20160929172322.GZ14933@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-09-29_11:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609020000 definitions=main-1609290302 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 29, 2016 at 06:10:37PM +0100, Will Deacon wrote: > On Thu, Sep 29, 2016 at 09:43:53AM -0700, Paul E. McKenney wrote: > > On Thu, Sep 29, 2016 at 05:03:08PM +0100, Will Deacon wrote: > > > On Thu, Sep 29, 2016 at 05:58:17PM +0200, Peter Zijlstra wrote: > > > > On Thu, Sep 29, 2016 at 08:54:01AM -0700, Paul E. McKenney wrote: > > > > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > > > > > broken if a third process overwrites the value written by the RELEASE > > > > > operation before the ACQUIRE operation has a chance of reading it. > > > > > This commit therefore updates the documentation to call this vulnerability > > > > > out explicitly. > > > > > > > > > > Reported-by: Alan Stern > > > > > Signed-off-by: Paul E. McKenney > > > > > > > > > + However, please note that a chain of RELEASE+ACQUIRE pairs may be > > > > > + broken by a store by another thread that overwrites the RELEASE > > > > > + operation's store before the ACQUIRE operation's read. > > > > > > > > This is the powerpc lwsync quirk, right? Where the barrier disappears > > > > when it looses the store. > > > > > > > > Or is there more to it? Its not entirely clear from the Changelog, which > > > > I feel should describe the reason for the behaviour. > > > > > > If I've groked it correctly, it's for cases like: > > > > > > > > > PO: > > > Wx=1 > > > WyRel=1 > > > > > > P1: > > > Wy=2 > > > > > > P2: > > > RyAcq=2 > > > Rx=0 > > > > > > Final value of y is 2. > > > > > > > > > This is permitted on arm64. If you make P1's store a store-release, then > > > it's forbidden, but I suspect that's not generally true of the kernel > > > memory model. > > > > That is the one! And to Peter's point, powerpc does the same for the > > example as shown. However, on powerpc, upgrading P1's store to release > > has no effect because there is no earlier access for the resulting > > lwsync to influence. For whatever it might be worth, C11 won't guarantee > > ordering in that case, either. Nor will the current Linux-kernel memory > > model. (Yes, I did just try it to make sure. Why do you ask?) > > > > So you guys are fishing for an expanded commit log, for example, like > > the following? ;-) > > > > Thanx, Paul > > > > ------------------------------------------------------------------------ > > > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > > broken if a third process overwrites the value written by the RELEASE > > operation before the ACQUIRE operation has a chance of reading it, for > > example: > > > > P0(int *x, int *y) > > { > > WRITE_ONCE(*x, 1); > > smp_wmb(); > > smp_store_release(y, 1); > > } > > > > P1(int *y) > > { > > smp_store_release(y, 2); > > } > > > > P2(int *x, int *y) > > { > > r1 = smp_load_acquire(y); > > r2 = READ_ONCE(*x); > > } > > > > Both ARM and powerpc allow the "after the dust settles" outcome (r1=2 && > > r2=0), as does the current version of the early prototype Linux-kernel > > memory model. > > FWIW, ARM doesn't allow this and arm64 only allows it if P1 uses WRITE_ONCE > instead of store-release. Good catch, apologies for the error. The following, then? Thanx, Paul ------------------------------------------------------------------------ If two processes are related by a RELEASE+ACQUIRE pair, ordering can be broken if a third process overwrites the value written by the RELEASE operation before the ACQUIRE operation has a chance of reading it, for example: P0(int *x, int *y) { WRITE_ONCE(*x, 1); smp_wmb(); smp_store_release(y, 1); } P1(int *y) { WRITE_ONCE(*y, 2); } P2(int *x, int *y) { r1 = smp_load_acquire(y); r2 = READ_ONCE(*x); } Both ARM and powerpc allow the "after the dust settles" outcome (r1=2 && r2=0), as does the current version of the early prototype Linux-kernel memory model.