From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752706AbcI3JUP (ORCPT ); Fri, 30 Sep 2016 05:20:15 -0400 Received: from foss.arm.com ([217.140.101.70]:39108 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752250AbcI3JUF (ORCPT ); Fri, 30 Sep 2016 05:20:05 -0400 Date: Fri, 30 Sep 2016 10:20:09 +0100 From: Will Deacon To: Boqun Feng Cc: "Paul E. McKenney" , Peter Zijlstra , linux-kernel@vger.kernel.org, mingo@kernel.org, dhowells@redhat.com, stern@rowland.harvard.edu Subject: Re: [PATCH locking/Documentation 1/2] Add note of release-acquire store vulnerability Message-ID: <20160930092009.GF10184@arm.com> References: <20160929155401.GA5097@linux.vnet.ibm.com> <20160929155817.GB5016@twins.programming.kicks-ass.net> <20160929160307.GT13862@arm.com> <20160929164353.GX14933@linux.vnet.ibm.com> <20160929171036.GV13862@arm.com> <20160929172322.GZ14933@linux.vnet.ibm.com> <20160930055352.GC22004@tardis.cn.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160930055352.GC22004@tardis.cn.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 30, 2016 at 01:53:52PM +0800, Boqun Feng wrote: > On Thu, Sep 29, 2016 at 10:23:22AM -0700, Paul E. McKenney wrote: > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > > broken if a third process overwrites the value written by the RELEASE > > operation before the ACQUIRE operation has a chance of reading it, for > > example: > > > > P0(int *x, int *y) > > { > > WRITE_ONCE(*x, 1); > > smp_wmb(); > ^^^^^^^^^^^ > > What is this smp_wmb() for? > > > smp_store_release(y, 1); > > } > > > > P1(int *y) > > { > > WRITE_ONCE(*y, 2); > > If we change this WRITE_ONCE to a relaxed atomic operation(e.g. > xchg_relaxed(y, 2)), both herd and ppcmem said the exist-clause "y = 2 > /\ 2:r1 = 2 /\ 2:r2 = 0" wouldn't be triggered on PPC. > > I guess we will get the same behavior on ARM/ARM64, Will? > > If a normal store could break chain, while a RmW atomic won't, do we > want to call it out in the document and build our memory model around > this? I think this is required to work by C11's definition of release sequences, so any architecture that claims to support those with the same instructions will need this to be forbidden. Personally, I think that's a bug in C11, because I think it goes too far in forbidding some hardware optimisations around relaxed xchg, but it is what it is. Will