From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753724AbcJDPBb (ORCPT ); Tue, 4 Oct 2016 11:01:31 -0400 Received: from down.free-electrons.com ([37.187.137.238]:33578 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751858AbcJDPB2 (ORCPT ); Tue, 4 Oct 2016 11:01:28 -0400 Date: Tue, 4 Oct 2016 10:02:45 +0200 From: Maxime Ripard To: Chen-Yu Tsai Cc: Linus Walleij , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 1/3] pinctrl: sunxi: Add support for fetching pinconf settings from hardware Message-ID: <20161004080245.GK5228@lukather> References: <20161004015112.20833-1-wens@csie.org> <20161004015112.20833-2-wens@csie.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="pP0ycGQONqsnqIMP" Content-Disposition: inline In-Reply-To: <20161004015112.20833-2-wens@csie.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --pP0ycGQONqsnqIMP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Oct 04, 2016 at 09:51:10AM +0800, Chen-Yu Tsai wrote: > The sunxi pinctrl driver only caches whatever pinconf setting was last > set on a given pingroup. This is not particularly helpful, nor is it > correct. >=20 > Fix this by actually reading the hardware registers and returning > the correct results or error codes. Also filter out unsupported > pinconf settings. Since this driver has a peculiar setup of 1 pin > per group, we can support both pin and pingroup pinconf setting > read back with the same code. The sunxi_pconf_reg helper and code > structure is inspired by pinctrl-msm. >=20 > With this done we can also claim to support generic pinconf, by > setting .is_generic =3D true in pinconf_ops. >=20 > Signed-off-by: Chen-Yu Tsai > --- > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 85 +++++++++++++++++++++++++++++= ++++-- > 1 file changed, 82 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunx= i/pinctrl-sunxi.c > index 54455af566ec..609843c9a65c 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -10,6 +10,7 @@ > * warranty of any kind, whether express or implied. > */ > =20 > +#include > #include > #include > #include > @@ -269,15 +270,91 @@ static const struct pinctrl_ops sunxi_pctrl_ops =3D= { > .get_group_pins =3D sunxi_pctrl_get_group_pins, > }; > =20 > +static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, > + u32 *offset, u32 *shift, u32 *mask) > +{ > + switch (param) { > + case PIN_CONFIG_DRIVE_STRENGTH: > + *offset =3D sunxi_dlevel_reg(pin); > + *shift =3D sunxi_dlevel_offset(pin); > + *mask =3D DLEVEL_PINS_MASK; > + break; > + > + case PIN_CONFIG_BIAS_PULL_UP: > + case PIN_CONFIG_BIAS_PULL_DOWN: > + case PIN_CONFIG_BIAS_DISABLE: > + *offset =3D sunxi_pull_reg(pin); > + *shift =3D sunxi_pull_offset(pin); > + *mask =3D PULL_PINS_MASK; > + break; > + > + default: > + return -ENOTSUPP; > + } > + > + return 0; > +} > + > +static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, > + unsigned long *config) > +{ > + struct sunxi_pinctrl *pctl =3D pinctrl_dev_get_drvdata(pctldev); > + enum pin_config_param param =3D pinconf_to_config_param(*config); > + u32 offset, shift, mask, val; > + u16 arg; > + int ret; > + > + pin -=3D pctl->desc->pin_base; > + > + ret =3D sunxi_pconf_reg(pin, param, &offset, &shift, &mask); > + if (ret < 0) > + return ret; > + > + val =3D (readl(pctl->membase + offset) >> shift) & mask; > + > + switch (pinconf_to_config_param(*config)) { > + case PIN_CONFIG_DRIVE_STRENGTH: > + arg =3D (val + 1) * 10; > + break; > + > + case PIN_CONFIG_BIAS_PULL_UP: > + if (val !=3D SUN4I_PINCTRL_PULL_UP) > + return -EINVAL; > + arg =3D 1; /* hardware is weak pull-up */ > + break; > + > + case PIN_CONFIG_BIAS_PULL_DOWN: > + if (val !=3D SUN4I_PINCTRL_PULL_DOWN) > + return -EINVAL; > + arg =3D 1; /* hardware is weak pull-down */ > + break; > + > + case PIN_CONFIG_BIAS_DISABLE: > + if (val !=3D SUN4I_PINCTRL_NO_PULL) > + return -EINVAL; > + arg =3D 0; > + break; > + > + default: > + /* sunxi_pconf_reg should catch anything unsupported */ > + WARN_ON(1); > + return -ENOTSUPP; This should be EINVAL. The operation is supported, but one of the argument is not valid. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --pP0ycGQONqsnqIMP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJX82IlAAoJEBx+YmzsjxAgpI0P/A2XUyLbrAuFFVIqBryUBV0G QUPl02bW+/Vj4yUDidvUXrrZn8JAdXh/cQw9NxLTK02MBBjrtr7nEn2cGOuKhU2k 8b01WjIiy6myNB68d9t93IYjYpHaxJmjbJ+Qsl6nFOCAsam0f4BWpGdhwNQXtC8p 1+MxFe1a9eJh3DE9NkZ1glEcy7deFUFg1T6WAr1pSRAkSVTHT/Yei88a0IEczJGE 2UkyX7Jo8bTJmB/Z6U0o0WX4Kce4nahY7gpIINdrbDvVnKRX3NVRZlmcwe388nt3 5SmADxofbsWqjeqUOUx8m1vF43vnYfs1WLD6FxKsG7wzHEYBNui57Zn9gadePv/a aznfEsJRT3gjNH0kd1AUoo1Kqji/bzSRTPPSSaZrf9KhTDSy42NZBis4jUiCmh+w LSn/OW+PsuJhCFgQIhCNFPiAgY9/tJNcyU8wsGkwWuYKDwOoB0jn2bS8/eAqS0v+ bwft25hRI0gbrcDd9in0zo32gC/oYmAWBlDacddvPZvUEGVEQQwEv1KFewKkzV4/ qzPKdjskbsspZlLMpERwkglLsc7EEBtgNV9gIRjxoG5PcWNyr82eg5xevW7CQfpt WQkiq/7grkOQZblTtCF4LH7yN3kMgeUtPRm4ghTAnmHl5gIFf6TeOSaBERDV0s4s 4J3tuO3/g1DMp+wxjJNp =eR8T -----END PGP SIGNATURE----- --pP0ycGQONqsnqIMP--