From: "Luck, Tony" <tony.luck@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
"H. Peter Anvin" <h.peter.anvin@intel.com>,
Ingo Molnar <mingo@elte.hu>,
Peter Zijlstra <peterz@infradead.org>,
Stephane Eranian <eranian@google.com>,
Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
Nilay Vaish <nilayvaish@gmail.com>, Shaohua Li <shli@fb.com>,
David Carrillo-Cisneros <davidcc@google.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Sai Prakhya <sai.praneeth.prakhya@intel.com>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system
Date: Mon, 17 Oct 2016 14:50:26 -0700 [thread overview]
Message-ID: <20161017215025.GA5702@intel.com> (raw)
In-Reply-To: <alpine.DEB.2.20.1610172157360.6407@nanos>
On Mon, Oct 17, 2016 at 11:14:55PM +0200, Thomas Gleixner wrote:
> > + /* Compute rdt_max_closid across all resources */
> > + rdt_max_closid = 0;
> > + for_each_rdt_resource(r)
> > + rdt_max_closid = max(rdt_max_closid, r->num_closid);
>
> Oh no! This needs to be min().
>
> Assume you have a system with L3 and L2 CAT. L2 reports COS_MAX=16, L3
> reports COS_MAX=16 as well. Then you enabled CDP which cuts L3 COS_MAX in
> half. So the real usable number of CLOSIDs is going to be 8 for both L2 and
> L3 simply because you do not have a seperation of L2 and L3 in
> MSR_PQR_ASSOC. And if you allow 16 then any CLOSID > 8 will result in
> undefined behaviour. See SDM:
>
> "When CDP is enabled, specifying a COS value in IA32_PQR_ASSOC.COS outside
> of the lower half of the COS space will cause undefined performance impact
> to code and data fetches due to MSR space re-indexing into code/data masks
> when CDP is enabled."
Bother. The SDM also has this gem:
17.17.5.1 Cache Allocation Technology Dynamic Configuration
Both the CAT masks and CQM registers are accessible and modifiable at
any time during execution using RDMSR/WRMSR unless otherwise noted. When
writing to these MSRs a #GP(0) will be generated if any of the following
conditions occur:
* Writing a COS greater than the supported maximum (specified as the
maximum value of CPUID.(EAX=10H, ECX=ResID):EDX[15:0] for all valid
ResID values) is written to the IA32_PQR_ASSOC.CLOS field.
With the intent here being that if you have more of one resource than
another, you can use all of the resources in the larger (with the
resource with fewer mask registers defaulting to the maximum value
when PQR_ASSOC.COS is too large [and I can't find the text that talks
about that default behaviour :-( ]
I think this all means that L3/CDP is "special". If CDP is on, we can't
use the top half of the CLOSID space that CPUID.(EAX=10H, ECX=1):EDX[15:0]
told us is present. So we can't exceed the half-way point. But in other
cases like L3 with max=16 and L2 with max=8 we should allow 16 groups,
but 0-7 allow control of L3 and L2, while 8-15 only allow L3 control (the
schemata code enforces this when you get to that part).
Perhaps we can encode this in another field in the rdt_resource structure
that says that some maximums globally override all others, while some
can be legitimately exceeded.
I'll have some words with the h/w architect, and get the SDM fixed in
the next edition.
-Tony
next prev parent reply other threads:[~2016-10-17 21:50 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-15 2:12 [PATCH v4 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-17 10:31 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-17 10:32 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-17 10:48 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-17 10:57 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-17 11:03 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-17 13:45 ` Thomas Gleixner
2016-10-17 18:06 ` Fenghua Yu
2016-10-17 16:35 ` Luck, Tony
2016-10-17 16:43 ` Yu, Fenghua
2016-10-17 20:20 ` Luck, Tony
2016-10-17 16:54 ` Thomas Gleixner
2016-10-17 16:53 ` Thomas Gleixner
2016-10-17 17:02 ` Thomas Gleixner
2016-10-17 21:22 ` Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-17 14:44 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-17 19:35 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-17 19:46 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-17 21:14 ` Thomas Gleixner
2016-10-17 21:50 ` Luck, Tony [this message]
2016-10-17 22:52 ` Thomas Gleixner
2016-10-17 23:00 ` Luck, Tony
2016-10-17 23:03 ` Thomas Gleixner
2016-10-17 23:10 ` Luck, Tony
2016-10-17 23:25 ` Thomas Gleixner
2016-10-18 1:18 ` Fenghua Yu
2016-10-17 23:20 ` Thomas Gleixner
2016-10-17 23:37 ` Luck, Tony
2016-10-18 2:56 ` Fenghua Yu
2016-10-18 10:44 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-17 21:27 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-17 22:01 ` Thomas Gleixner
2016-10-17 22:17 ` Luck, Tony
2016-10-15 2:12 ` [PATCH v4 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-17 22:35 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
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