From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757524AbcJXMGr (ORCPT ); Mon, 24 Oct 2016 08:06:47 -0400 Received: from mail.kernel.org ([198.145.29.136]:40680 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756858AbcJXMGq (ORCPT ); Mon, 24 Oct 2016 08:06:46 -0400 Date: Mon, 24 Oct 2016 20:06:21 +0800 From: Shawn Guo To: Stefan Agner Cc: kernel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: dts: vf610: fix IRQ flag of global timer Message-ID: <20161024120621.GI30578@tiger> References: <20161018015127.16981-1-stefan@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161018015127.16981-1-stefan@agner.ch> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 17, 2016 at 06:51:27PM -0700, Stefan Agner wrote: > The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a > rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter > 10.1.2. Interrupt types and sources says: > "Interrupt is rising-edge sensitive." > > The bits seem to be read-only, hence this missconfiguration had > no negative effect. However, with commit 992345a58e0c > ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") > warnings such as this get printed: > GIC: PPI11 is secure or misconfigured > > With this change the new configuration matches the default > configuration and no warning is printed anymore. > > Signed-off-by: Stefan Agner Applied, thanks.