From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755683AbcJZVzF (ORCPT ); Wed, 26 Oct 2016 17:55:05 -0400 Received: from mga11.intel.com ([192.55.52.93]:37257 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754281AbcJZVy6 (ORCPT ); Wed, 26 Oct 2016 17:54:58 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,551,1473145200"; d="scan'208";a="24137783" Date: Wed, 26 Oct 2016 14:54:45 -0700 From: Fenghua Yu To: Thomas Gleixner Cc: Fenghua Yu , "H. Peter Anvin" , Ingo Molnar , Tony Luck , Peter Zijlstra , Stephane Eranian , Borislav Petkov , Dave Hansen , Nilay Vaish , Shaohua Li , David Carrillo-Cisneros , Ravi V Shankar , Sai Prakhya , Vikas Shivappa , linux-kernel , x86 Subject: Re: [PATCH v5 00/18] Intel Cache Allocation Technology Message-ID: <20161026215445.GC1752@linux.intel.com> References: <1477142405-32078-1-git-send-email-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 26, 2016 at 11:39:47PM +0200, Thomas Gleixner wrote: > On Sat, 22 Oct 2016, Fenghua Yu wrote: > > This version should cover all comments from Thomas. > > Emphasis on should :) > > But this series is a major step forward and I decided to merge the first > lot: > > > 0001-Documentation-ABI-Add-a-document-entry-for-cache-id.patch > > 0002-cacheinfo-Introduce-cache-id.patch > > 0003-x86-intel_cacheinfo-Enable-cache-id-in-x86.patch > > 0004-x86-intel_rdt-Feature-discovery.patch > > > 0006-x86-intel_rdt-Add-CONFIG-Makefile-and-basic-initiali.patch > > 0007-x86-intel_rdt-Add-Haswell-feature-discovery.patch > > 0008-x86-intel_rdt-Pick-up-L3-L2-RDT-parameters-from-CPUID.patch > > 0009-x86-cqm-Move-PQR_ASSOC-management-code-into-generic-.patch > > I fixed up #0004 (including Borislavs comments) and polished some of the > changelogs a bit. > > This reduces the size of the series and prevents that these parts get > [un]intentionally fat fingered once again. > > I intentionally left out the documentation patch as that one needs to be > updated when you address the max closid issues. > > Please work against tip x86/cache from now on. > > The remaining issues are not that big, so I think we are really close. > > Thanks > > tglx This is really great! I'm working on releasing updated remaining patches based on the tip x86/cache. Thank you, Thomas! -Fenghua