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Date: Fri, 18 Nov 2016 11:07:53 +0200
From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Tan Jui Nee <jui.nee.tan@intel.com>
Cc: heikki.krogerus@linux.intel.com, andriy.shevchenko@linux.intel.com,
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Subject: Re: [PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to
 Sideband bridge support driver for Intel SOC's
Message-ID: <20161118090753.GV1446@lahna.fi.intel.com>
References: <1479446550-28677-1-git-send-email-jui.nee.tan@intel.com>
 <1479446550-28677-2-git-send-email-jui.nee.tan@intel.com>
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On Fri, Nov 18, 2016 at 01:22:25PM +0800, Tan Jui Nee wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> There is already one and at least one more user coming which
> require an access to Primary to Sideband bridge (P2SB) in order
> to get IO or MMIO bar hidden by BIOS.
> Create a driver to access P2SB for x86 devices.
> 
> Signed-off-by: Yong, Jonathan <jonathan.yong@intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>