From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753492AbcLFOIn (ORCPT ); Tue, 6 Dec 2016 09:08:43 -0500 Received: from merlin.infradead.org ([205.233.59.134]:36712 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752475AbcLFOIl (ORCPT ); Tue, 6 Dec 2016 09:08:41 -0500 Date: Tue, 6 Dec 2016 13:38:48 +0100 From: Peter Zijlstra To: Andi Kleen Cc: linux-kernel@vger.kernel.org, Andi Kleen , alexander.shishkin@intel.com, kan.liang@intel.com, stable@vger.kernel.org Subject: Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Message-ID: <20161206123848.GS3207@twins.programming.kicks-ass.net> References: <20161202231732.25478-1-andi@firstfloor.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161202231732.25478-1-andi@firstfloor.org> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some reason this patch never hit my inbox, it could be because you're wrecked the Cc line and either infradead or my mta dropped the email because of that. On Fri, Dec 02, 2016 at 03:17:32PM -0800, Andi Kleen wrote: > From: Andi Kleen > > The earlier patch ccbebba4 allowed enabling PT and LBR at the same SHAs should be 12 chars. > time on Goldmont. However it also allowed enabling BTS and LBR > at the same time, which is still not supported. Fix this by > bypassing the check only for PT. > > Marking for stable because this allows crashing kernels. Also > should be merged for 4.9. > > Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") same > Cc: alexander.shishkin@intel.com > Cc: kan.liang@intel.com > Cc: stable@vger.kernel.org # 4.6+ > Signed-off-by: Andi Kleen > --- > arch/x86/events/core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index d0efb5cb1b00..baa1eed55e88 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what) > { > int i; > > - if (x86_pmu.lbr_pt_coexist) > + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist) > return 0; This would also allow PT & BTS at the same time, is that a supported configuration? > > if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {