From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934052AbdADKYo (ORCPT ); Wed, 4 Jan 2017 05:24:44 -0500 Received: from foss.arm.com ([217.140.101.70]:47860 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751148AbdADKYm (ORCPT ); Wed, 4 Jan 2017 05:24:42 -0500 Date: Wed, 4 Jan 2017 10:23:45 +0000 From: Mark Rutland To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, kim.phillips@arm.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, tglx@linutronix.de, peterz@infradead.org, alexander.shishkin@linux.intel.com, robh@kernel.org, suzuki.poulose@arm.com, pawel.moll@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 01/10] arm64: cpufeature: allow for version discrepancy in PMU implementations Message-ID: <20170104102345.GB8329@leverpostej> References: <1483467027-14547-1-git-send-email-will.deacon@arm.com> <1483467027-14547-2-git-send-email-will.deacon@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1483467027-14547-2-git-send-email-will.deacon@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 03, 2017 at 06:10:18PM +0000, Will Deacon wrote: > Perf already supports multiple PMU instances for heterogeneous systems, > so there's no need to be strict in the cpufeature checking, particularly > as the PMU extension is optional in the architecture. > > Reviewed-by: Suzuki K Poulose > Signed-off-by: Will Deacon There are remaining issues with PMU support exposed to KVM guests in hetereogeneous systems, but I think that's a larger issue with KVM and heterogeneous CPUs (and we're already aware of it), so FWIW: Acked-by: Mark Rutland Thanks, Mark. > --- > arch/arm64/kernel/cpufeature.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index fdf8f045929f..47d0226620e8 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -184,7 +184,11 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { > ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), > - S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), > + /* > + * We can instantiate multiple PMU instances with different levels > + * of support. > + * */ > + S_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), > ARM64_FTR_END, > -- > 2.1.4 >