From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752606AbdAUAwG (ORCPT ); Fri, 20 Jan 2017 19:52:06 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:59832 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752327AbdAUAwE (ORCPT ); Fri, 20 Jan 2017 19:52:04 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A0748609FC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 20 Jan 2017 16:52:02 -0800 From: Stephen Boyd To: Markus Mayer Cc: Michael Turquette , Rob Herring , Mark Rutland , Viresh Kumar , "Rafael J . Wysocki" , Arnd Bergmann , Markus Mayer , Broadcom Kernel List , Linux Clock List , Power Management List , Device Tree List , ARM Kernel List , Linux Kernel Mailing List Subject: Re: [PATCH v5 1/2] dt-bindings: brcm: clocks: add binding for brcmstb-cpu-clk-div Message-ID: <20170121005202.GB8801@codeaurora.org> References: <20170119002933.7529-1-code@mmayer.net> <20170119002933.7529-2-code@mmayer.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170119002933.7529-2-code@mmayer.net> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/18, Markus Mayer wrote: > diff --git a/Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt b/Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt > new file mode 100644 > index 0000000..c4acb53 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt > @@ -0,0 +1,27 @@ > +The CPU divider node serves as the sole clock for the CPU complex. It supports > +power-of-2 clock division, with a divider of "1" as the default highest-speed > +setting. > + > +Required properties: > +- compatible: shall be "brcm,brcmstb-cpu-clk-div" > +- reg: address and width of the divider configuration register > +- #clock-cells: shall be set to 0 > +- clocks: phandle of clock provider which provides the source clock > + (this would typically be a "fixed-clock" type PLL) > +- div-table: list of (raw_value,divider) ordered pairs that correspond to the > + allowed clock divider settings > +- div-shift-width: least-significant bit position and width of divider value Are these properties used? Please don't put these types of details in DT. > + > +Optional properties: > +- clock-names: the clock may be named > + > +Example: > + cpuclkdiv: cpu-clk-div@f03e257c { > + compatible = "brcm,brcmstb-cpu-clk-div"; > + reg = <0xf03e257c 0x4>; This register really looks like some offset in something larger. Is there some clock controller? What's the hw block at 0xf03e2000? Maybe I already asked this. > + div-table = <0x00 1>; > + div-shift-width = <0 5>; > + #clock-cells = <0>; > + clocks = <&cpupll>; > + clock-names = "cpupll"; > + }; > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project