From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751282AbdAWMdi (ORCPT ); Mon, 23 Jan 2017 07:33:38 -0500 Received: from bombadil.infradead.org ([65.50.211.133]:42602 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751130AbdAWMdh (ORCPT ); Mon, 23 Jan 2017 07:33:37 -0500 Date: Mon, 23 Jan 2017 13:33:30 +0100 From: Peter Zijlstra To: Suravee Suthikulpanit Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, joro@8bytes.org, bp@alien8.de, mingo@redhat.com Subject: Re: [PATCH v8 3/9] perf/amd/iommu: Misc fix up perf_iommu_read Message-ID: <20170123123330.GY6485@twins.programming.kicks-ass.net> References: <1484551416-5440-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1484551416-5440-4-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1484551416-5440-4-git-send-email-Suravee.Suthikulpanit@amd.com> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 16, 2017 at 01:23:30AM -0600, Suravee Suthikulpanit wrote: > static void perf_iommu_read(struct perf_event *event) > { > - u64 count = 0ULL; > - u64 prev_raw_count = 0ULL; > - u64 delta = 0ULL; > + u64 count, prev; > + s64 delta; I did send that email where I told I was mistaken with that suggestion, right? Since the counter always increments (it does, right), a negative delta does not make sense. > struct hw_perf_event *hwc = &event->hw; > > amd_iommu_pc_get_set_reg_val(_GET_DEVID(event), > @@ -330,18 +329,20 @@ static void perf_iommu_read(struct perf_event *event) > IOMMU_PC_COUNTER_REG, &count, false); > > /* IOMMU pc counter register is only 48 bits */ > - count &= 0xFFFFFFFFFFFFULL; > + count &= GENMASK_ULL(48, 0); Why do you need that at all? If the counter is only 48 bits, what does the hardware do with the upper bits? > > - prev_raw_count = local64_read(&hwc->prev_count); > - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, > - count) != prev_raw_count) > - return; > + prev = local64_read(&hwc->prev_count); I'm still not convinced you can do away with that cmpxchg. > > - /* Handling 48-bit counter overflowing */ > - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT); > + /* > + * Since we do not enable counter overflow interrupts, > + * we do not have to worry about prev_count changing on us. > + */ > + local64_set(&hwc->prev_count, count); > + > + /* Handle 48-bit counter overflow */ > + delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); > delta >>= COUNTER_SHIFT; > local64_add(delta, &event->count); > - > } > > static void perf_iommu_stop(struct perf_event *event, int flags) > -- > 1.8.3.1 >