From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750970AbdA0S4I (ORCPT ); Fri, 27 Jan 2017 13:56:08 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:58736 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750708AbdA0Szf (ORCPT ); Fri, 27 Jan 2017 13:55:35 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6C019609FF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 27 Jan 2017 10:48:09 -0800 From: Stephen Boyd To: Chris Packham Cc: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, Michael Turquette , Rob Herring , Mark Rutland , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC Message-ID: <20170127184809.GE8801@codeaurora.org> References: <20170127032546.14657-1-chris.packham@alliedtelesis.co.nz> <20170127032546.14657-2-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170127032546.14657-2-chris.packham@alliedtelesis.co.nz> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/27, Chris Packham wrote: > The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from > the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. > > The clock gating options are a subset of those on the Armada XP. > > The core clock divider is different to the Armada XP also. > > Signed-off-by: Chris Packham > Acked-by: Rob Herring > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project