From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754073AbdA3SUe (ORCPT ); Mon, 30 Jan 2017 13:20:34 -0500 Received: from mail-qt0-f172.google.com ([209.85.216.172]:34753 "EHLO mail-qt0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753600AbdA3SUd (ORCPT ); Mon, 30 Jan 2017 13:20:33 -0500 Date: Mon, 30 Jan 2017 13:20:30 -0500 From: Sean Paul To: John Keeping Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 09/24] drm/rockchip: dw-mipi-dsi: only request HS clock when required Message-ID: <20170130182030.GJ20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-10-john@metanate.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170129132444.25251-10-john@metanate.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jan 29, 2017 at 01:24:29PM +0000, John Keeping wrote: > Requesting the HS clock from the PHY before we initialize it causes an > invalid signal to be sent out since the input clock is not yet > configured. The PHY databook suggests only asserting this signal when > performing HS transfers, so let's do that. > Reviewed-by: Sean Paul > Signed-off-by: John Keeping > Reviewed-by: Chris Zhong > --- > v3: > - Add Chris' Reviewed-by > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 15d33c3c8cb7..03fc096fe1bd 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,13 +545,15 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, > const struct mipi_dsi_msg *msg) > { > + bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; > u32 val = 0; > > if (msg->flags & MIPI_DSI_MSG_REQ_ACK) > val |= EN_ACK_RQST; > - if (msg->flags & MIPI_DSI_MSG_USE_LPM) > + if (lpm) > val |= CMD_MODE_ALL_LP; > > + dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_CMD_MODE_CFG, val); > } > > @@ -693,6 +695,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, > dsi_write(dsi, DSI_PWR_UP, RESET); > dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); > dw_mipi_dsi_video_mode_config(dsi); > + dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_PWR_UP, POWERUP); > } > } > @@ -710,7 +713,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > | PHY_RSTZ | PHY_SHUTDOWNZ); > dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | > TX_ESC_CLK_DIVIDSION(7)); > - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > } > > static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS