From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752125AbdAaMhM (ORCPT ); Tue, 31 Jan 2017 07:37:12 -0500 Received: from dougal.metanate.com ([90.155.101.14]:37686 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752006AbdAaMg5 (ORCPT ); Tue, 31 Jan 2017 07:36:57 -0500 Date: Tue, 31 Jan 2017 12:14:09 +0000 From: John Keeping To: Sean Paul Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling Message-ID: <20170131121409.4cc453d0.john@metanate.com> In-Reply-To: <20170130202808.GR20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-16-john@metanate.com> <20170130202808.GR20076@art_vandelay> Organization: Metanate Ltd X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 30 Jan 2017 15:28:08 -0500, Sean Paul wrote: > On Sun, Jan 29, 2017 at 01:24:35PM +0000, John Keeping wrote: > > The bias, bandgap and PLL should all be configured before we enable > > them. > > > > Do you know why the test codes are hard-coded magic? It'd be nice to make some > sense of them in a future patch. I just kept with the existing style of the code, but it should be straightforward to add some defines with sensible names. > Reviewed-by: Sean Paul > > > Signed-off-by: John Keeping > > --- > > v3: > > - Squash together two patches that both affect initialization order of > > the PHY > > Unchanged in v2 > > > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++----- > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > index 5b3068e9e8db..cfe7e4ba305c 100644 > > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > > > dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); > > > > - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > > dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); > > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | > > LOW_PROGRAM_EN); > > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | > > HIGH_PROGRAM_EN); > > + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > > + > > + dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > > + BIASEXTR_SEL(BIASEXTR_127_7)); > > + dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | > > + BANDGAP_SEL(BANDGAP_96_10)); > > > > dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | > > BIAS_BLOCK_ON | BANDGAP_ON); > > @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > SETRD_MAX | POWER_MANAGE | > > TER_RESISTORS_ON); > > > > - dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > > - BIASEXTR_SEL(BIASEXTR_127_7)); > > - dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | > > - BANDGAP_SEL(BANDGAP_96_10)); > > > > dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > > dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > > -- > > 2.11.0.197.gb556de5.dirty > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel >