From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752731AbdBJIvN (ORCPT ); Fri, 10 Feb 2017 03:51:13 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:35440 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752075AbdBJIvL (ORCPT ); Fri, 10 Feb 2017 03:51:11 -0500 Date: Fri, 10 Feb 2017 09:50:28 +0100 From: Ingo Molnar To: kan.liang@intel.com Cc: peterz@infradead.org, linux-kernel@vger.kernel.org, eranian@google.com, ak@linux.intel.com Subject: Re: [PATCH] x86, perf: Add Top Down events to Intel Goldmont Message-ID: <20170210085028.GA6570@gmail.com> References: <1486650998-78800-1-git-send-email-kan.liang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1486650998-78800-1-git-send-email-kan.liang@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * kan.liang@intel.com wrote: > From: Kan Liang > > Goldmont supports full Top Down level 1 metrics (FrontendBound, > Retiring, Backend Bound and Bad Speculation). > It has 3 wide pipeline. > > Signed-off-by: Kan Liang > --- > arch/x86/events/intel/core.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index eb1484c..baaac28 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -1553,6 +1553,31 @@ static __initconst const u64 slm_hw_cache_event_ids > }, > }; > > +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); > +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); > +/* UOPS_NOT_DELIVERED.ANY */ > +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, > + "event=0x9c"); > +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ > +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, > + "event=0xca,umask=0x02"); > +/* UOPS_RETIRED.ANY */ > +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, > + "event=0xc2"); > +/* UOPS_ISSUED.ANY */ > +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, > + "event=0x0e"); Please don't break lines in funny places and make code unreadable. Instead have a look at the existing event listing style in arch/x86/events/intel/core.c and match that! Ok? Thanks, Ingo