From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752394AbdBOVUF (ORCPT ); Wed, 15 Feb 2017 16:20:05 -0500 Received: from mail-it0-f41.google.com ([209.85.214.41]:34851 "EHLO mail-it0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751063AbdBOVUC (ORCPT ); Wed, 15 Feb 2017 16:20:02 -0500 Date: Wed, 15 Feb 2017 14:19:58 -0700 From: Mathieu Poirier To: Leo Yan Cc: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Thompson Subject: Re: [PATCH RFC 3/3] arm64: dts: register Hi6220's coresight debug module Message-ID: <20170215211958.GC29730@linaro.org> References: <1486966298-16767-1-git-send-email-leo.yan@linaro.org> <1486966298-16767-4-git-send-email-leo.yan@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1486966298-16767-4-git-send-email-leo.yan@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 13, 2017 at 02:11:38PM +0800, Leo Yan wrote: > Bind coresight debug driver for Hi6220. Bindings for the coresight debug driver... > > Signed-off-by: Leo Yan > --- > .../boot/dts/hisilicon/hikey_6220_coresight.dtsi | 73 ++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi > index 77c2aab..e14d75c 100644 > --- a/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi > @@ -15,6 +15,79 @@ > #size-cells = <2>; > compatible = "arm,amba-bus"; > ranges; > + > + debug@0,f6590000 { Simply use "debug@f6590000", the "0," isn't required. > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6590000 0 0x1000>; > + default_enable; What is the "default_enable" for ? > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu0>; > + }; > + > + debug@1,f6592000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6592000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu1>; > + }; > + > + debug@2,f6594000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6594000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu2>; > + }; > + > + debug@3,f6596000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6596000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu3>; > + }; > + > + debug@4,f65d0000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d0000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu4>; > + }; > + > + debug@5,f65d2000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d2000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu5>; > + }; > + > + debug@6,f65d4000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d4000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu6>; > + }; > + > + debug@7,f65d6000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d6000 0 0x1000>; > + default_enable; > + clocks = <&sys_ctrl HI6220_CS_ATB>; > + clock-names = "apb_pclk"; > + cpu = <&cpu7>; > + }; > + > etm@0,f659c000 { > compatible = "arm,coresight-etm4x","arm,primecell"; > reg = <0 0xf659c000 0 0x1000>; > -- > 2.7.4 >