From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933831AbdBQKtz convert rfc822-to-8bit (ORCPT ); Fri, 17 Feb 2017 05:49:55 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:53352 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932674AbdBQKtv (ORCPT ); Fri, 17 Feb 2017 05:49:51 -0500 Date: Fri, 17 Feb 2017 18:44:51 +0800 From: Jisheng Zhang To: Gregory CLEMENT CC: , , , , , Subject: Re: [PATCH net-next v2 0/2] net: mvneta: improve rx performance Message-ID: <20170217184451.55217e0e@xhacker> In-Reply-To: <87shndayse.fsf@free-electrons.com> References: <20170217100233.2325-1-jszhang@marvell.com> <87shndayse.fsf@free-electrons.com> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-02-17_08:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702170103 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 17 Feb 2017 11:37:21 +0100 Gregory CLEMENT wrote: > Hi Jisheng, > > On ven., févr. 17 2017, Jisheng Zhang wrote: > > > In hot code path such as mvneta_rx_hwbm() and mvneta_rx_swbm(), we may > > access fields of rx_desc. The rx_desc is allocated by > > dma_alloc_coherent, it's uncacheable if the device isn't cache > > coherent, reading from uncached memory is fairly slow. > > Did you test it with HWBM support? No I didn't test it for lacking of such HW, so it's appreciated if someone can test with HWBM capable HW. > > I am not sure ti will work in this case. IMHO, if mvneta HW doesn't update rx_desc->buf_phys_addr, it can still work. I don't have HWBM background, so above may be wrong. If this case doesn't work for HWBM, I'll submit v3 to modify mvneta_rx_swbm() only. Thanks, Jisheng > > Gregory > > > > > patch1 reuses the read out status to getting status field of rx_desc > > again. > > > > patch2 uses cacheable memory to store the rx buffer DMA address. > > > > We get the following performance data on Marvell BG4CT Platforms > > (tested with iperf): > > > > before the patch: > > recving 1GB in mvneta_rx_swbm() costs 149265960 ns > > > > after the patch: > > recving 1GB in mvneta_rx_swbm() costs 1421565640 ns > > > > We saved 4.76% time. > > > > RFC: can we do similar modification for tx? If yes, I can prepare a v2. > > > > > > Basically, these two patches do what Arnd mentioned in [1]. > > > > Hi Arnd, > > > > I added "Suggested-by you" tag, I hope you don't mind ;) > > > > Thanks > > > > [1] https://www.spinics.net/lists/netdev/msg405889.html > > > > Since v1: > > - correct the performance data typo > > > > Jisheng Zhang (2): > > net: mvneta: avoid getting status from rx_desc as much as possible > > net: mvneta: Use cacheable memory to store the rx buffer DMA address > > > > drivers/net/ethernet/marvell/mvneta.c | 36 ++++++++++++++++++++--------------- > > 1 file changed, 21 insertions(+), 15 deletions(-) > > > > -- > > 2.11.0 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >