From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753380AbdBTM66 (ORCPT ); Mon, 20 Feb 2017 07:58:58 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:42925 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752562AbdBTM6z (ORCPT ); Mon, 20 Feb 2017 07:58:55 -0500 From: Jisheng Zhang To: , , , , CC: , , , Jisheng Zhang Subject: [PATCH net-next v3 0/4] net: mvneta: improve rx/tx performance Date: Mon, 20 Feb 2017 20:53:40 +0800 Message-ID: <20170220125344.3555-1-jszhang@marvell.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-02-20_11:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702200127 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In hot code path such as mvneta_rx_swbm(), we access fields of rx_desc and tx_desc. These DMA descs are allocated by dma_alloc_coherent, they are uncacheable if the device isn't cache coherent, reading from uncached memory is fairly slow. patch1 reuses the read out status to getting status field of rx_desc again. patch2 avoids getting buf_phys_addr from rx_desc again in mvneta_rx_hwbm by reusing the phys_addr variable. patch3 avoids reading from tx_desc as much as possible by store what we need in local variable. We get the following performance data on Marvell BG4CT Platforms (tested with iperf): before the patch: sending 1GB in mvneta_tx()(disabled TSO) costs 793553760ns after the patch: sending 1GB in mvneta_tx()(disabled TSO) costs 719953800ns we saved 9.2% time. patch4 uses cacheable memory to store the rx buffer DMA address. We get the following performance data on Marvell BG4CT Platforms (tested with iperf): before the patch: recving 1GB in mvneta_rx_swbm() costs 1492659600 ns after the patch: recving 1GB in mvneta_rx_swbm() costs 1421565640 ns We saved 4.76% time. Basically, patch1 and patch4 do what Arnd mentioned in [1]. Hi Arnd, I added "Suggested-by you" tag, I hope you don't mind ;) Thanks [1] https://www.spinics.net/lists/netdev/msg405889.html Since v2: - add Gregory's ack to patch1 - only get rx buffer DMA address from cacheable memory for mvneta_rx_swbm() - add patch 2 to read rx_desc->buf_phys_addr once in mvneta_rx_hwbm() - add patch 3 to avoid reading from tx_desc as much as possible Since v1: - correct the performance data typo Jisheng Zhang (4): net: mvneta: avoid getting status from rx_desc as much as possible net: mvneta: avoid getting buf_phys_addr from rx_desc again net: mvneta: avoid reading from tx_desc as much as possible net: mvneta: Use cacheable memory to store the rx buffer DMA address drivers/net/ethernet/marvell/mvneta.c | 80 +++++++++++++++++++---------------- 1 file changed, 43 insertions(+), 37 deletions(-) -- 2.11.0