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Date: Wed, 1 Mar 2017 11:44:02 +0530
From: Viresh Kumar <viresh.kumar@linaro.org>
To: Rob Herring <robh@kernel.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
        Rafael Wysocki <rjw@rjwysocki.net>, Kevin Hilman <khilman@linaro.org>,
        Viresh Kumar <vireshk@kernel.org>, Nishanth Menon <nm@ti.com>,
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        Vincent Guittot <vincent.guittot@linaro.org>,
        Lina Iyer <lina.iyer@linaro.org>,
        Rajendra Nayak <rnayak@codeaurora.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH V3 2/7] PM / OPP: Introduce "domain-performance-state"
 binding to OPP nodes
Message-ID: <20170301061402.GE24323@vireshk-i7>
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On 28-02-17, 09:52, Rob Herring wrote:
> On Tue, Feb 28, 2017 at 9:14 AM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> > This comes from the early design of the generic PM domain, thus I
> > assume we have some HW with such complex PM topology. However, I don't
> > know if it is actually being used.
> >
> > Moreover, the corresponding DT bindings for "power-domains" parents,
> > can easily be extended to cover more than one parent. See more in
> > Documentation/devicetree/bindings/power/power_domain.txt
> 
> I could easily see device having 2 power domains. For example a cpu
> may have separate domains for RAM/caches and logic.

An important thing here is that PM domain doesn't support such devices. i.e. a
device isn't allowed to have multiple PM domains today. So a way to support such
devices can be to create a virtual PM domain, that has two parents and device as
its child.

-- 
viresh