Re: [PATCH v11 7/9] mmc: cavium: Add scatter-gather DMA support

kbuild test robot
2017-02-12T01:27:43Z

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Hi Jan,

[auto build test ERROR on linus/master]
[also build test ERROR on v4.10-rc7 next-20170210]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Jan-Glauber/Cavium-MMC-driver/20170206-214740
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64

All errors (new ones prefixed by >>):

arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:255:29: note: in expansion of macro 'readq'
old_slot->cached_switch = readq(host->base + MIO_EMM_SWITCH);
^~~~~
drivers/mmc/host/cavium-mmc.c:256:45: error: 'MIO_EMM_RCA' undeclared (first use in this function)
old_slot->cached_rca = readq(host->base + MIO_EMM_RCA);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:256:26: note: in expansion of macro 'readq'
old_slot->cached_rca = readq(host->base + MIO_EMM_RCA);
^~~~~
In file included from include/linux/scatterlist.h:8:0,
from include/linux/dma-mapping.h:10,
from drivers/mmc/host/cavium-mmc.c:18:
drivers/mmc/host/cavium-mmc.c:267:38: error: 'MIO_EMM_SAMPLE' undeclared (first use in this function)
writeq(emm_sample.val, host->base + MIO_EMM_SAMPLE);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:267:2: note: in expansion of macro 'writeq'
writeq(emm_sample.val, host->base + MIO_EMM_SAMPLE);
^~~~~~
drivers/mmc/host/cavium-mmc.c: In function 'do_read':
drivers/mmc/host/cavium-mmc.c:281:47: error: 'MIO_EMM_BUF_IDX' undeclared (first use in this function)
writeq((0x10000 | (dbuf << 6)), host->base + MIO_EMM_BUF_IDX);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:281:2: note: in expansion of macro 'writeq'
writeq((0x10000 | (dbuf << 6)), host->base + MIO_EMM_BUF_IDX);
^~~~~~
In file included from include/linux/swab.h:4:0,
from include/uapi/linux/byteorder/big_endian.h:12,
from include/linux/byteorder/big_endian.h:4,
from arch/arm64/include/uapi/asm/byteorder.h:20,
from include/asm-generic/bitops/le.h:5,
from arch/arm64/include/asm/bitops.h:50,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/delay.h:10,
from drivers/mmc/host/cavium-mmc.c:16:
drivers/mmc/host/cavium-mmc.c:291:29: error: 'MIO_EMM_BUF_DAT' undeclared (first use in this function)
dat = readq(host->base + MIO_EMM_BUF_DAT);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:291:10: note: in expansion of macro 'readq'
dat = readq(host->base + MIO_EMM_BUF_DAT);
^~~~~
drivers/mmc/host/cavium-mmc.c: In function 'set_cmd_response':
drivers/mmc/host/cavium-mmc.c:322:30: error: 'MIO_EMM_RSP_LO' undeclared (first use in this function)
rsp_lo = readq(host->base + MIO_EMM_RSP_LO);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:322:11: note: in expansion of macro 'readq'
rsp_lo = readq(host->base + MIO_EMM_RSP_LO);
^~~~~
drivers/mmc/host/cavium-mmc.c:335:31: error: 'MIO_EMM_RSP_HI' undeclared (first use in this function)
rsp_hi = readq(host->base + MIO_EMM_RSP_HI);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:335:12: note: in expansion of macro 'readq'
rsp_hi = readq(host->base + MIO_EMM_RSP_HI);
^~~~~
drivers/mmc/host/cavium-mmc.c: In function 'finish_dma_sg':
>> drivers/mmc/host/cavium-mmc.c:359:40: error: 'MIO_EMM_DMA_FIFO_CFG' undeclared (first use in this function)
fifo_cfg.val = readq(host->dma_base + MIO_EMM_DMA_FIFO_CFG);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:359:17: note: in expansion of macro 'readq'
fifo_cfg.val = readq(host->dma_base + MIO_EMM_DMA_FIFO_CFG);
^~~~~
drivers/mmc/host/cavium-mmc.c: In function 'cleanup_dma':
drivers/mmc/host/cavium-mmc.c:397:35: error: 'MIO_EMM_DMA' undeclared (first use in this function)
emm_dma.val = readq(host->base + MIO_EMM_DMA);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:397:16: note: in expansion of macro 'readq'
emm_dma.val = readq(host->base + MIO_EMM_DMA);
^~~~~
drivers/mmc/host/cavium-mmc.c: In function 'cvm_mmc_interrupt':
drivers/mmc/host/cavium-mmc.c:419:35: error: 'MIO_EMM_INT' undeclared (first use in this function)
emm_int.val = readq(host->base + MIO_EMM_INT);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:419:16: note: in expansion of macro 'readq'
emm_int.val = readq(host->base + MIO_EMM_INT);
^~~~~
drivers/mmc/host/cavium-mmc.c:429:35: error: 'MIO_EMM_RSP_STS' undeclared (first use in this function)
rsp_sts.val = readq(host->base + MIO_EMM_RSP_STS);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:429:16: note: in expansion of macro 'readq'
rsp_sts.val = readq(host->base + MIO_EMM_RSP_STS);
^~~~~
In file included from include/linux/scatterlist.h:8:0,
from include/linux/dma-mapping.h:10,
from drivers/mmc/host/cavium-mmc.c:18:
drivers/mmc/host/cavium-mmc.c: In function 'prepare_dma_single':
drivers/mmc/host/cavium-mmc.c:508:39: error: 'MIO_EMM_DMA_CFG' undeclared (first use in this function)
writeq(dma_cfg.val, host->dma_base + MIO_EMM_DMA_CFG);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:508:2: note: in expansion of macro 'writeq'
writeq(dma_cfg.val, host->dma_base + MIO_EMM_DMA_CFG);
^~~~~~
drivers/mmc/host/cavium-mmc.c:514:33: error: 'MIO_EMM_DMA_ADR' undeclared (first use in this function)
writeq(addr, host->dma_base + MIO_EMM_DMA_ADR);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:514:3: note: in expansion of macro 'writeq'
writeq(addr, host->dma_base + MIO_EMM_DMA_ADR);
^~~~~~
drivers/mmc/host/cavium-mmc.c: In function 'prepare_dma_sg':
drivers/mmc/host/cavium-mmc.c:537:29: error: 'MIO_EMM_DMA_FIFO_CFG' undeclared (first use in this function)
writeq(0, host->dma_base + MIO_EMM_DMA_FIFO_CFG);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:537:2: note: in expansion of macro 'writeq'
writeq(0, host->dma_base + MIO_EMM_DMA_FIFO_CFG);
^~~~~~
>> drivers/mmc/host/cavium-mmc.c:544:33: error: 'MIO_EMM_DMA_FIFO_ADR' undeclared (first use in this function)
writeq(addr, host->dma_base + MIO_EMM_DMA_FIFO_ADR);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:544:3: note: in expansion of macro 'writeq'
writeq(addr, host->dma_base + MIO_EMM_DMA_FIFO_ADR);
^~~~~~
>> drivers/mmc/host/cavium-mmc.c:568:41: error: 'MIO_EMM_DMA_FIFO_CMD' undeclared (first use in this function)
writeq(fifo_cmd.val, host->dma_base + MIO_EMM_DMA_FIFO_CMD);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:568:3: note: in expansion of macro 'writeq'
writeq(fifo_cmd.val, host->dma_base + MIO_EMM_DMA_FIFO_CMD);
^~~~~~
drivers/mmc/host/cavium-mmc.c: In function 'cvm_mmc_dma_request':
drivers/mmc/host/cavium-mmc.c:683:38: error: 'MIO_EMM_STS_MASK' undeclared (first use in this function)
writeq(0x00b00000ull, host->base + MIO_EMM_STS_MASK);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:683:3: note: in expansion of macro 'writeq'
writeq(0x00b00000ull, host->base + MIO_EMM_STS_MASK);
^~~~~~
drivers/mmc/host/cavium-mmc.c:686:35: error: 'MIO_EMM_DMA' undeclared (first use in this function)
writeq(emm_dma.val, host->base + MIO_EMM_DMA);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:686:2: note: in expansion of macro 'writeq'
writeq(emm_dma.val, host->base + MIO_EMM_DMA);
^~~~~~
drivers/mmc/host/cavium-mmc.c: In function 'do_write_request':
drivers/mmc/host/cavium-mmc.c:714:34: error: 'MIO_EMM_BUF_IDX' undeclared (first use in this function)
writeq(0x10000ull, host->base + MIO_EMM_BUF_IDX);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:714:2: note: in expansion of macro 'writeq'
writeq(0x10000ull, host->base + MIO_EMM_BUF_IDX);
^~~~~~
drivers/mmc/host/cavium-mmc.c:731:29: error: 'MIO_EMM_BUF_DAT' undeclared (first use in this function)
writeq(dat, host->base + MIO_EMM_BUF_DAT);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:731:4: note: in expansion of macro 'writeq'
writeq(dat, host->base + MIO_EMM_BUF_DAT);
^~~~~~
drivers/mmc/host/cavium-mmc.c: In function 'cvm_mmc_request':
drivers/mmc/host/cavium-mmc.c:800:25: error: 'MIO_EMM_STS_MASK' undeclared (first use in this function)
writeq(0, host->base + MIO_EMM_STS_MASK);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:800:2: note: in expansion of macro 'writeq'
writeq(0, host->base + MIO_EMM_STS_MASK);
^~~~~~
In file included from include/linux/swab.h:4:0,
from include/uapi/linux/byteorder/big_endian.h:12,
from include/linux/byteorder/big_endian.h:4,
from arch/arm64/include/uapi/asm/byteorder.h:20,
from include/asm-generic/bitops/le.h:5,
from arch/arm64/include/asm/bitops.h:50,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/delay.h:10,
from drivers/mmc/host/cavium-mmc.c:16:
drivers/mmc/host/cavium-mmc.c:803:35: error: 'MIO_EMM_RSP_STS' undeclared (first use in this function)
rsp_sts.val = readq(host->base + MIO_EMM_RSP_STS);
^
include/uapi/linux/swab.h:129:32: note: in definition of macro '__swab64'
(__builtin_constant_p((__u64)(x)) ? \
^
include/linux/byteorder/generic.h:86:21: note: in expansion of macro '__le64_to_cpu'
#define le64_to_cpu __le64_to_cpu
^~~~~~~~~~~~~
arch/arm64/include/asm/io.h:137:32: note: in expansion of macro 'readq_relaxed'
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
drivers/mmc/host/cavium-mmc.c:803:16: note: in expansion of macro 'readq'
rsp_sts.val = readq(host->base + MIO_EMM_RSP_STS);
^~~~~
In file included from include/linux/scatterlist.h:8:0,
from include/linux/dma-mapping.h:10,
from drivers/mmc/host/cavium-mmc.c:18:
drivers/mmc/host/cavium-mmc.c:812:35: error: 'MIO_EMM_CMD' undeclared (first use in this function)
writeq(emm_cmd.val, host->base + MIO_EMM_CMD);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
drivers/mmc/host/cavium-mmc.c:812:2: note: in expansion of macro 'writeq'
writeq(emm_cmd.val, host->base + MIO_EMM_CMD);
^~~~~~
drivers/mmc/host/cavium-mmc.c: In function 'cvm_mmc_init_lowlevel':
drivers/mmc/host/cavium-mmc.c:914:43: error: 'MIO_EMM_CFG' undeclared (first use in this function)
writeq(host->emm_cfg, slot->host->base + MIO_EMM_CFG);
^
arch/arm64/include/asm/io.h:127:78: note: in definition of macro 'writeq_relaxed'
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
^
..

vim +/MIO_EMM_DMA_FIFO_CFG +359 drivers/mmc/host/cavium-mmc.c

329 req->cmd->resp[2] = 0;
330 req->cmd->resp[3] = 0;
331 break;
332 case 2:
333 req->cmd->resp[3] = rsp_lo & 0xffffffff;
334 req->cmd->resp[2] = (rsp_lo >> 32) & 0xffffffff;
> 335 rsp_hi = readq(host->base + MIO_EMM_RSP_HI);
336 req->cmd->resp[1] = rsp_hi & 0xffffffff;
337 req->cmd->resp[0] = (rsp_hi >> 32) & 0xffffffff;
338 break;
339 }
340 }
341
342 static int get_dma_dir(struct mmc_data *data)
343 {
344 return (data->flags & MMC_DATA_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
345 }
346
347 static int finish_dma_single(struct cvm_mmc_host *host, struct mmc_data *data)
348 {
349 data->bytes_xfered = data->blocks * data->blksz;
350 data->error = 0;
351 return 1;
352 }
353
354 static int finish_dma_sg(struct cvm_mmc_host *host, struct mmc_data *data)
355 {
356 union mio_emm_dma_fifo_cfg fifo_cfg;
357
358 /* Check if there are any pending requests left */
> 359 fifo_cfg.val = readq(host->dma_base + MIO_EMM_DMA_FIFO_CFG);
360 if (fifo_cfg.s.count)
361 dev_err(host->dev, "%u requests still pending\n",
362 fifo_cfg.s.count);
363
364 data->bytes_xfered = data->blocks * data->blksz;
365 data->error = 0;
366
367 /* Clear and disable FIFO */
368 writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG);
369 dma_unmap_sg(host->dev, data->sg, data->sg_len, get_dma_dir(data));
370 return 1;
371 }
372
373 static int finish_dma(struct cvm_mmc_host *host, struct mmc_data *data)
374 {
375 if (host->use_sg && data->sg_len > 1)
376 return finish_dma_sg(host, data);
377 else
378 return finish_dma_single(host, data);
379 }
380
381 static bool bad_status(union mio_emm_rsp_sts *rsp_sts)
382 {
383 if (rsp_sts->s.rsp_bad_sts || rsp_sts->s.rsp_crc_err ||
384 rsp_sts->s.rsp_timeout || rsp_sts->s.blk_crc_err ||
385 rsp_sts->s.blk_timeout || rsp_sts->s.dbuf_err)
386 return true;
387
388 return false;
389 }
390
391 /* Try to clean up failed DMA. */
392 static void cleanup_dma(struct cvm_mmc_host *host,
393 union mio_emm_rsp_sts *rsp_sts)
394 {
395 union mio_emm_dma emm_dma;
396
397 emm_dma.val = readq(host->base + MIO_EMM_DMA);
398 emm_dma.s.dma_val = 1;
399 emm_dma.s.dat_null = 1;
400 emm_dma.s.bus_id = rsp_sts->s.bus_id;
401 writeq(emm_dma.val, host->base + MIO_EMM_DMA);
402 }
403
404 irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id)
405 {
406 struct cvm_mmc_host *host = dev_id;
407 union mio_emm_rsp_sts rsp_sts;
408 union mio_emm_int emm_int;
409 struct mmc_request *req;
410 unsigned long flags = 0;
411 bool host_done;
412
413 if (host->need_irq_handler_lock)
414 spin_lock_irqsave(&host->irq_handler_lock, flags);
415 else
416 __acquire(&host->irq_handler_lock);
417
418 /* Clear interrupt bits (write 1 clears ). */
419 emm_int.val = readq(host->base + MIO_EMM_INT);
420 writeq(emm_int.val, host->base + MIO_EMM_INT);
421
422 if (emm_int.s.switch_err)
423 check_switch_errors(host);
424
425 req = host->current_req;
426 if (!req)
427 goto out;
428
429 rsp_sts.val = readq(host->base + MIO_EMM_RSP_STS);
430 /*
431 * dma_val set means DMA is still in progress. Don't touch
432 * the request and wait for the interrupt indicating that
433 * the DMA is finished.
434 */
435 if (rsp_sts.s.dma_val && host->dma_active)
436 goto out;
437
438 if (!host->dma_active && emm_int.s.buf_done && req->data) {
439 unsigned int type = (rsp_sts.val >> 7) & 3;
440
441 if (type == 1)
442 do_read(host, req, rsp_sts.s.dbuf);
443 else if (type == 2)
444 do_write(req);
445 }
446
447 host_done = emm_int.s.cmd_done || emm_int.s.dma_done ||
448 emm_int.s.cmd_err || emm_int.s.dma_err;
449
450 if (!(host_done && req->done))
451 goto no_req_done;
452
453 if (bad_status(&rsp_sts))
454 req->cmd->error = -EILSEQ;
455 else
456 req->cmd->error = 0;
457
458 if (host->dma_active && req->data)
459 if (!finish_dma(host, req->data))
460 goto no_req_done;
461
462 set_cmd_response(host, req, &rsp_sts);
463 if (emm_int.s.dma_err && rsp_sts.s.dma_pend)
464 cleanup_dma(host, &rsp_sts);
465
466 host->current_req = NULL;
467 req->done(req);
468
469 no_req_done:
470 if (host->dmar_fixup_done)
471 host->dmar_fixup_done(host);
472 if (host_done)
473 host->release_bus(host);
474 out:
475 if (host->need_irq_handler_lock)
476 spin_unlock_irqrestore(&host->irq_handler_lock, flags);
477 else
478 __release(&host->irq_handler_lock);
479 return IRQ_RETVAL(emm_int.val != 0);
480 }
481
482 /*
483 * Program DMA_CFG and if needed DMA_ADR.
484 * Returns 0 on error, DMA address otherwise.
485 */
486 static u64 prepare_dma_single(struct cvm_mmc_host *host, struct mmc_data *data)
487 {
488 union mio_emm_dma_cfg dma_cfg;
489 int count;
490 u64 addr;
491
492 count = dma_map_sg(host->dev, data->sg, data->sg_len,
493 get_dma_dir(data));
494 if (!count)
495 return 0;
496
497 dma_cfg.val = 0;
498 dma_cfg.s.en = 1;
499 dma_cfg.s.rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
500 #ifdef __LITTLE_ENDIAN
501 dma_cfg.s.endian = 1;
502 #endif
503 dma_cfg.s.size = (sg_dma_len(&data->sg[0]) / 8) - 1;
504
505 addr = sg_dma_address(&data->sg[0]);
506 if (!host->big_dma_addr)
507 dma_cfg.s.adr = addr;
508 writeq(dma_cfg.val, host->dma_base + MIO_EMM_DMA_CFG);
509
510 pr_debug("[%s] sg_dma_len: %u total sg_elem: %d\n",
511 (dma_cfg.s.rw) ? "W" : "R", sg_dma_len(&data->sg[0]), count);
512
513 if (host->big_dma_addr)
514 writeq(addr, host->dma_base + MIO_EMM_DMA_ADR);
515 return addr;
516 }
517
518 /*
519 * Queue complete sg list into the FIFO.
520 * Returns 0 on error, 1 otherwise.
521 */
522 static u64 prepare_dma_sg(struct cvm_mmc_host *host, struct mmc_data *data)
523 {
524 union mio_emm_dma_fifo_cmd fifo_cmd;
525 struct scatterlist *sg;
526 int count, i;
527 u64 addr;
528
529 count = dma_map_sg(host->dev, data->sg, data->sg_len,
530 get_dma_dir(data));
531 if (!count)
532 return 0;
533 if (count > 16)
534 goto error;
535
536 /* Enable FIFO by removing CLR bit */
> 537 writeq(0, host->dma_base + MIO_EMM_DMA_FIFO_CFG);
538
539 for_each_sg(data->sg, sg, count, i) {
540 /* Program DMA address */
541 addr = sg_dma_address(sg);
542 if (addr & 7)
543 goto error;
> 544 writeq(addr, host->dma_base + MIO_EMM_DMA_FIFO_ADR);
545
546 /*
547 * If we have scatter-gather support we also have an extra

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0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

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