From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754057AbdDJN0P (ORCPT ); Mon, 10 Apr 2017 09:26:15 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60738 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753805AbdDJN0M (ORCPT ); Mon, 10 Apr 2017 09:26:12 -0400 Date: Mon, 10 Apr 2017 15:26:10 +0200 From: Boris Brezillon To: Linus Walleij Cc: Simon Hatliff , Alexandre Courbot , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Thomas Petazzoni Subject: Re: [PATCH 1/2] gpio: Add a driver for Cadence GPIO controller Message-ID: <20170410152610.58bc589a@bbrezillon> In-Reply-To: <3422ee23-53b5-8d09-2a5e-d700358ab09d@cadence.com> References: <1490803459-29697-1-git-send-email-boris.brezillon@free-electrons.com> <20170330132946.41314874@bbrezillon> <3422ee23-53b5-8d09-2a5e-d700358ab09d@cadence.com> X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 30 Mar 2017 18:26:01 +0100 Simon Hatliff wrote: > Hi Boris, Linus, > > On 30/03/17 12:29, Boris Brezillon wrote: > > Hi Linus, > > > > On Thu, 30 Mar 2017 11:03:45 +0200 > > Linus Walleij wrote: > > > >> On Wed, Mar 29, 2017 at 6:04 PM, Boris Brezillon > >> wrote: > >> > >>> Add a driver for Cadence GPIO controller. > >> IIUC Cadence do a lot of things. Are there variants of this controller? > > I'll let Simon answer that one. > This is a controller that has been around since 2000. It is not > configurable in any way, so there are no variants. Cadence do not offer > any other GPIO controllers as IP. > >>> +static irqreturn_t cdns_gpio_irq_handler(int irq, void *dev) > >>> +{ > >>> + struct cdns_gpio_chip *cgpio = dev; > >>> + unsigned long status; > >>> + int hwirq; > >>> + > >>> + /* > >>> + * FIXME: If we have an edge irq that is masked we might lose it > >>> + * since reading the STATUS register clears all IRQ flags. > >>> + * We could store the status of all masked IRQ in the cdns_gpio_chip > >>> + * struct but we then have no way to re-trigger the interrupt when > >>> + * it is unmasked. > >>> + */ > >> It is marked FIXME but do you think it can even be fixed? It seems > >> like a hardware flaw. :( > > Maybe not. Unless Simon comes up with a magic register to re-trigger an > > interrupt :-). > There are no plans to update the controller. Linus, what should I do here? Drop support for edge interrupts?