From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756260AbdDRJ5r (ORCPT ); Tue, 18 Apr 2017 05:57:47 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:40680 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753784AbdDRJ5n (ORCPT ); Tue, 18 Apr 2017 05:57:43 -0400 Date: Tue, 18 Apr 2017 11:57:41 +0200 From: Maxime Ripard To: Chen-Yu Tsai Cc: David Airlie , dri-devel , linux-sunxi , linux-arm-kernel , linux-kernel Subject: Re: [PATCH 09/11] drm/sun4i: Support two display pipelines Message-ID: <20170418095741.dfay2drvyiwpmlyl@lukather> References: <20170309100534.14023-1-wens@csie.org> <20170309100534.14023-10-wens@csie.org> <20170309103636.j5jtjhwjztzchr6u@lukather> <20170309144009.kgixcnrjg4cot6ut@lukather> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="sz2trmbxlcdqvtfn" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --sz2trmbxlcdqvtfn Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Chen-Yu, On Sat, Apr 08, 2017 at 01:30:55AM +0800, Chen-Yu Tsai wrote: > Hi, >=20 > On Thu, Mar 9, 2017 at 10:40 PM, Maxime Ripard > wrote: > > On Thu, Mar 09, 2017 at 07:20:30PM +0800, Chen-Yu Tsai wrote: > >> On Thu, Mar 9, 2017 at 6:36 PM, Maxime Ripard > >> wrote: > >> > Hi, > >> > > >> > On Thu, Mar 09, 2017 at 06:05:32PM +0800, Chen-Yu Tsai wrote: > >> >> Some Allwinner SoCs have two display pipelines (frontend -> backend= -> > >> >> tcon). > >> >> > >> >> Previously we only supported one pipeline. This patch extends the > >> >> current driver to support two. It extends the tcon and backend poin= ters > >> >> in sun4i_drv into arrays, and makes the related bind functions store > >> >> the pointer into said arrays based on the id fetched from the device > >> >> tree. In the case of the tcons, it falls back to a first come order > >> >> if no encoders that can be used for differentiating the tcons are > >> >> defined. The driver's depth-first traversal of the of graph, coupled > >> >> with the increasing address ordering of the of graph endpoints, and > >> >> the fact that tcon0 should always be enabled for the tcon/encoder > >> >> mux to be accessible, means that tcon1 would always come after tcon= 0. > >> >> > >> >> Assignment of the device structure into sun4i_drv is moved to the e= nd > >> >> of the bind function, when all possible error checks have passed. > >> >> > >> >> This patch also drops a trailing 0 in one of the backend probe mess= ages. > >> >> > >> >> Signed-off-by: Chen-Yu Tsai > >> >> --- > >> >> drivers/gpu/drm/sun4i/sun4i_backend.c | 9 +++++++-- > >> >> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +- > >> >> drivers/gpu/drm/sun4i/sun4i_drv.h | 6 ++++-- > >> >> drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +++++++++++++++++------= -- > >> >> 4 files changed, 29 insertions(+), 13 deletions(-) > >> >> > >> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/dr= m/sun4i/sun4i_backend.c > >> >> index f3c92d54c8e4..8d22efd5a9cc 100644 > >> >> --- a/drivers/gpu/drm/sun4i/sun4i_backend.c > >> >> +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c > >> >> @@ -350,12 +350,15 @@ static int sun4i_backend_bind(struct device *= dev, struct device *master, > >> >> if (!backend) > >> >> return -ENOMEM; > >> >> dev_set_drvdata(dev, backend); > >> >> - drv->backend =3D backend; > >> >> > >> >> backend->id =3D sun4i_backend_of_get_id(dev->of_node); > >> >> if (backend->id < 0) > >> >> return backend->id; > >> >> > >> >> + /* We only support SUN4I_DRM_MAX_PIPELINES number of backends= */ > >> >> + if (backend->id >=3D SUN4I_DRM_MAX_PIPELINES) > >> >> + return -EINVAL; > >> >> + > >> >> res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > >> >> regs =3D devm_ioremap_resource(dev, res); > >> >> if (IS_ERR(regs)) > >> >> @@ -364,7 +367,7 @@ static int sun4i_backend_bind(struct device *de= v, struct device *master, > >> >> backend->regs =3D devm_regmap_init_mmio(dev, regs, > >> >> &sun4i_backend_regmap_c= onfig); > >> >> if (IS_ERR(backend->regs)) { > >> >> - dev_err(dev, "Couldn't create the backend0 regmap\n"); > >> >> + dev_err(dev, "Couldn't create the backend regmap\n"); > >> >> return PTR_ERR(backend->regs); > >> >> } > >> >> > >> >> @@ -413,6 +416,8 @@ static int sun4i_backend_bind(struct device *de= v, struct device *master, > >> >> } > >> >> } > >> >> > >> >> + drv->backend[backend->id] =3D backend; > >> >> + > >> >> /* Reset the registers */ > >> >> for (i =3D 0x800; i < 0x1000; i +=3D 4) > >> >> regmap_write(backend->regs, i, 0); > >> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/su= n4i/sun4i_drv.c > >> >> index 767bbadcc85d..c15ecb8343d7 100644 > >> >> --- a/drivers/gpu/drm/sun4i/sun4i_drv.c > >> >> +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c > >> >> @@ -271,7 +271,7 @@ static int sun4i_drv_probe(struct platform_devi= ce *pdev) > >> >> struct device_node *np =3D pdev->dev.of_node; > >> >> int i, count =3D 0; > >> >> > >> >> - for (i =3D 0;; i++) { > >> >> + for (i =3D 0; i < SUN4I_DRM_MAX_PIPELINES; i++) { > >> >> struct device_node *pipeline =3D of_parse_phandle(np, > >> >> "allw= inner,pipelines", > >> >> i); > >> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.h b/drivers/gpu/drm/su= n4i/sun4i_drv.h > >> >> index 5df50126ff52..ec1c08af47e1 100644 > >> >> --- a/drivers/gpu/drm/sun4i/sun4i_drv.h > >> >> +++ b/drivers/gpu/drm/sun4i/sun4i_drv.h > >> >> @@ -16,9 +16,11 @@ > >> >> #include > >> >> #include > >> >> > >> >> +#define SUN4I_DRM_MAX_PIPELINES 2 > >> >> + > >> >> struct sun4i_drv { > >> >> - struct sun4i_backend *backend; > >> >> - struct sun4i_tcon *tcon; > >> >> + struct sun4i_backend *backend[SUN4I_DRM_MAX_PIPELINES]; > >> >> + struct sun4i_tcon *tcon[SUN4I_DRM_MAX_PIPELINES]; > >> >> > >> >> struct drm_fbdev_cma *fbdev; > >> >> }; > >> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/s= un4i/sun4i_tcon.c > >> >> index b774c9a50c55..7749c3133f38 100644 > >> >> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > >> >> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > >> >> @@ -532,7 +532,6 @@ static int sun4i_tcon_bind(struct device *dev, = struct device *master, > >> >> if (!tcon) > >> >> return -ENOMEM; > >> >> dev_set_drvdata(dev, tcon); > >> >> - drv->tcon =3D tcon; > >> >> tcon->drm =3D drm; > >> >> tcon->dev =3D dev; > >> >> tcon->quirks =3D of_device_get_match_data(dev); > >> >> @@ -540,14 +539,22 @@ static int sun4i_tcon_bind(struct device *dev= , struct device *master, > >> >> /* This can fail if the DT does not have any downstream encod= ers. */ > >> >> tcon->id =3D sun4i_tcon_of_get_id(dev->of_node); > >> >> if (tcon->id < 0) { > >> >> - /* > >> >> - * TODO We currently support only 1 TCON, so we can > >> >> - * safely set this to 0. This should be revisited > >> >> - * when we add support for multiple pipelines. > >> >> - */ > >> >> - tcon->id =3D 0; > >> >> + int i; > >> >> + > >> >> + /* find the first empty tcon in sun4i_drv */ > >> >> + for (i =3D 0; i < SUN4I_DRM_MAX_PIPELINES; i++) > >> >> + if (!drv->tcon[i]) > >> >> + tcon->id =3D i; > >> >> + > >> >> + /* bail out if that failed */ > >> >> + if (tcon->id < 0) > >> >> + return tcon->id; > >> >> } > >> >> > >> >> + /* We only support SUN4I_DRM_MAX_PIPELINES number of tcons */ > >> >> + if (tcon->id >=3D SUN4I_DRM_MAX_PIPELINES) > >> >> + return -EINVAL; > >> >> + > >> >> tcon->lcd_rst =3D devm_reset_control_get(dev, "lcd"); > >> >> if (IS_ERR(tcon->lcd_rst)) { > >> >> dev_err(dev, "Couldn't get our reset line\n"); > >> >> @@ -588,7 +595,7 @@ static int sun4i_tcon_bind(struct device *dev, = struct device *master, > >> >> goto err_free_dotclock; > >> >> } > >> >> > >> >> - tcon->crtc =3D sun4i_crtc_init(drm, drv->backend, tcon); > >> >> + tcon->crtc =3D sun4i_crtc_init(drm, drv->backend[tcon->id], t= con); > >> > > >> > I'm not a big fan of those IDs. The heuristic seems to be a bit > >> > fragile since we really never enforced any order in our bindings. > >> > >> Yes. I seem to have forgotten that bit which I had intended to add. > >> The endpoint IDs would ideally match the actual mux values used. > > > > That works for me, but the binding documentation would need to be > > amended. > > > >> On the TCON side that's not doable, so we might have to just require > >> them being in an increasing order. > > > > What are you planning to use those IDs on for the TCON? >=20 > This reply sat in my draft box for way too long. >=20 > As mentioned, the IDs on the TCON side are for the IDing the TV encoders. > I think having the IDs for the same type of encoder be increasing, such > that the endpoint for TV encoder 1 has a higher ID than the one for TV > encoder 0 should be enough. There aren't any other instances where we > have 2 or more of the same type. Or we could just add some kind of index > property to the TV encoder node. This is for the A20 by the way. Sorry if I'm missing a bit of context here, but I still don't get *why* you would need to ID them. So far, your explanation seems to have been "so that we can ID them", which is pretty circular to me :) > >> > You seem to use it for two things: > >> > - to match a TCON to its backend in our code > >> > - to not step on each others' toes when registering the backends/tc= ons > >> > > >> > I think the second could be easily addressed using a linked list, and > >> > the first one by storing the of_node. Then we just need to follow the > >> > OF graph to our input of_node, and then iterate through our register= ed > >> > backend list to find the one with the same of_node. > >> > >> Yes that would work for the above purposes. > >> > >> For getting the first TCON to access the mux registers, it kind of fal= ls > >> short. We also need something like this for the TV encoders on A10/A20. > >> They too have a mux, which seems to be in the first TV encoder. This > >> controls how the 8 DACs are mapped to the 4 external pins. > > > > How are those pins muxed between the two? Can't we just create a > > connector that would be usable for both encoders? >=20 > They are freely muxable. However if you want VGA output, you need 3 pins > for RGB from the same TV encoder, plus H/V sync from it's upstream TCON. (you don't really need hsync and vsync on VGA, those are optional signals) > And you have one pin left that you can use for composite, which would > likely be fed from the other TCON, as you need interlaced YUV data, > which is like the opposite of VGA. I'm not sure how these muxers should be implemented in DRM. One trivial way would be to have a small pinctrl driver in the TCON driver to deal with that, and switch states in both TV encoders at runtime (if needed, statically otherwise). Or maybe we can do something simpler, I don't know. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --sz2trmbxlcdqvtfn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJY9eMNAAoJEBx+YmzsjxAgbF4QAIslpcBVAzEcQZm2OfK5RASh /HRmJ16MVLNqNRvEfz+h+YXzNzFNdfboGDoVZyKFQ++7AjcyjAxgL5sIjE/nYhfm zLa0YtZ9hHZp1fPnlVx3NwaMHK5D6O5TGNeCX3I5KM7h9al8Uih06qxLMDQs+hPk SSgaUG8dWECdpvJqtIry7U4lBIgwOiE9OiaGIZPDaayt3LqkAabrzB4h9X84dXKF ZWLZAjXy+pSAksmjfK4qw5cFRjaRnzH5JJCl4gdX5YcUn+DPtsEO7GAYZEuRHXlL OfPtBPPYaYa/gIC+2Mr5ezRTN6b+VrUv7aup1SplBXVOR0EW0JTtNDPMdX3W7Uwp gUJQJFQ+RZzPjAWXE6G7DXY64IlesU8B1/VGep/ji1aCrhAQrZy0cGYUfoKnXAhZ LjP28D4k4qEVbUAa4VIcNW32XeH0Reab+ihQbrMYP6+Xzi4qwKQGDXWdArcyreAT TCm2B86XsnabNEoxsQ5kRV0HaTCT7jMmJuPmzb9kOIM+D8PoH3WLEuj6bGoTXzrf /oYT9EnR+zjuFoU0ahRZrK9sR2hO0vPn8U/maDlh/sX7WHIy5w3ZSFQt2QQjFks6 81Gr8MAhIkHBomsRoIgVc86SR5BG/vDhQ3hUBlbpj9CLKFh/Mjx6mPgjR2sV25PB PZLnAxj+LBvX4XkXnjaE =2a3l -----END PGP SIGNATURE----- --sz2trmbxlcdqvtfn--