From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S939338AbdD1ORu (ORCPT ); Fri, 28 Apr 2017 10:17:50 -0400 Received: from foss.arm.com ([217.140.101.70]:49582 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938127AbdD1ORp (ORCPT ); Fri, 28 Apr 2017 10:17:45 -0400 Date: Fri, 28 Apr 2017 15:17:45 +0100 From: Will Deacon To: Catalin Marinas Cc: Florian Fainelli , Mark Rutland , opendmb@gmail.com, Peter Zijlstra , alcooperx@gmail.com, "open list:PERFORMANCE EVENTS SUBSYSTEM" , Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Message-ID: <20170428141745.GQ13675@arm.com> References: <20170420190546.7453-1-f.fainelli@gmail.com> <20170420190546.7453-4-f.fainelli@gmail.com> <20170425124427.GI24484@arm.com> <28edde78-b965-8136-1c95-11b9182de405@gmail.com> <20170427173642.GM1890@arm.com> <20170428141500.GE6368@e104818-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170428141500.GE6368@e104818-lin.cambridge.arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 28, 2017 at 03:15:01PM +0100, Catalin Marinas wrote: > On Thu, Apr 27, 2017 at 06:36:42PM +0100, Will Deacon wrote: > > On Tue, Apr 25, 2017 at 10:13:51AM -0700, Florian Fainelli wrote: > > > On 04/25/2017 05:44 AM, Will Deacon wrote: > > > > On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote: > > > >> The ARMv8 PMUv3 cache map did not include the L2 cache events, add > > > >> them. > > > >> > > > >> Signed-off-by: Florian Fainelli > > > >> --- > > > >> arch/arm64/kernel/perf_event.c | 5 +++++ > > > >> 1 file changed, 5 insertions(+) > > > >> > > > >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > > > >> index 4f011cdd756d..a664c575f3fd 100644 > > > >> --- a/arch/arm64/kernel/perf_event.c > > > >> +++ b/arch/arm64/kernel/perf_event.c > > > >> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] > > > >> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, > > > >> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, > > > >> > > > >> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, > > > >> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, > > > >> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, > > > >> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, > > > > > > > > I don't think this is correct in general. 'LL' stands for "last-level", > > > > which may be L3 or even a system cache in the interconnect. Tying that to L2 > > > > is the wrong thing to do from perf's generic event perspective. > > > > > > > > I'm ok with what you're proposing for A53 (where the PMU can only count > > > > events out to the L2), but I'm reluctant to make this change for the generic > > > > PMUv3 events. > > > > > > That makes sense, shall I resubmit the first patch by itself or can you > > > or Catalin take it as-is? > > > > I'll talk to Catalin tomorrow and try to get the A53 bit queued. > > I queued patch 1/2. Shall I add your ack? Yes, please. Will