From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751342AbdEBQPf (ORCPT ); Tue, 2 May 2017 12:15:35 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:34422 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751014AbdEBQPe (ORCPT ); Tue, 2 May 2017 12:15:34 -0400 Date: Tue, 2 May 2017 09:15:30 -0700 From: Brian Norris To: Boris Brezillon Cc: Christophe LEROY , Richard Weinberger , David Woodhouse , Marek Vasut , Cyrille Pitchen , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mtd: nand: gpio: make nCE GPIO optional Message-ID: <20170502161530.GA26931@google.com> References: <20170210140110.87903682E7@localhost.localdomain> <20170501214627.GB140640@google.com> <20170502110334.33f1a3b8@bbrezillon> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170502110334.33f1a3b8@bbrezillon> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Christophe, Boris, On Tue, May 02, 2017 at 11:03:34AM +0200, Boris Brezillon wrote: > On Tue, 2 May 2017 07:47:40 +0200 > Christophe LEROY wrote: > > > Le 01/05/2017 à 23:46, Brian Norris a écrit : > > > On Fri, Feb 10, 2017 at 03:01:10PM +0100, Christophe Leroy wrote: > > >> On some hardware, the nCE signal is wired to the ChipSelect associated > > >> to bus address of the NAND, so it is automatically driven during the > > >> memory access and it is not managed by a GPIO. > > >> > > >> Signed-off-by: Christophe Leroy > > > > > > Not really a problem with this patch exactly, but FYI you're only making > > > this optional for the non-DT case. For device tree, this is kinda hard > > > to do, since the current binding suggests we retrieve the GPIOs based on > > > index position, not by name. So if you leave one off...I guess we well > > > just be off-by-1 on the indeces until we hit a non-optional one...which > > > I guess is "CLE". > > > > > > If we wanted this to work for DT, we'd need to extend this driver (and > > > binding doc) to support requesting GPIOs by name. > > > > > > > It works for me with devicetree. > > > > I have the following definition in my DT: > > > > nand@1,0 { > > compatible = "gpio-control-nand"; > > reg = <1 0x0 0x01>; > > #address-cells = <1>; > > #size-cells = <1>; > > gpios = <&qe_pio_c 24 1 // RDY > > 0 // nCE > > &qe_pio_c 26 1 // ALE > > &qe_pio_c 25 1 // CLE > > 0>; // nwp > > }; > > > > Yep, it's perfectly fine to have 'empty' gpio entries (entries with > phandle set to 0/NULL), we're using this trick in the atmel_nand > driver as well. I wasn't aware. In that case, you need to change the binding doc to note that nCE is optional now. Brian