* [PATCH 0/4] staging: rtl8723bs: resolve checkpatch issues
@ 2017-05-12 1:45 Matthew Giassa
2017-05-12 1:45 ` [PATCH 1/4] staging: rtl8723bs: checkpatch - remove multiple blank lines Matthew Giassa
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Matthew Giassa @ 2017-05-12 1:45 UTC (permalink / raw)
To: gregkh; +Cc: hdegoede, devel, linux-kernel, matthew
This set of patches resolves a large number of non-functional issues
reported by checkpatch for the following header:
drivers/staging/rtl8723bs/include/rtl8723b_spec.h
*Typos in comments
*Indentation consistency (original code not formatted for 8-wide
hard-tabs) and 80+ column width lines.
*Multiple blank lines
*Mixed space/hard-tab indentation
All outstanding checkpatch errors/warnings/checks are resolved by this
series of patches.
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/4] staging: rtl8723bs: checkpatch - remove multiple blank lines 2017-05-12 1:45 [PATCH 0/4] staging: rtl8723bs: resolve checkpatch issues Matthew Giassa @ 2017-05-12 1:45 ` Matthew Giassa 2017-05-12 1:45 ` [PATCH 2/4] staging: rtl8723bs: checkpatch - remove mixed spaces/hard-tabs Matthew Giassa ` (2 subsequent siblings) 3 siblings, 0 replies; 10+ messages in thread From: Matthew Giassa @ 2017-05-12 1:45 UTC (permalink / raw) To: gregkh; +Cc: hdegoede, devel, linux-kernel, matthew Resolving checkpatch issue: CHECK: Please don't use multiple blank lines All instances resolved. --- drivers/staging/rtl8723bs/include/rtl8723b_spec.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h index 8d78f4e..960d8e4 100644 --- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h +++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h @@ -17,7 +17,6 @@ #include <autoconf.h> - #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ /* */ @@ -124,7 +123,6 @@ /* */ /* */ - /* */ /* SDIO Bus Specification */ /* */ @@ -142,7 +140,6 @@ /* */ #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ - /* */ /* 8723 Regsiter Bit and Content definition */ /* */ @@ -161,7 +158,6 @@ /* */ /* */ - /* */ /* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ @@ -207,7 +203,6 @@ #define EEPROM_RF_GAIN_OFFSET 0xC1 #define EEPROM_RF_GAIN_VAL 0x1F6 - /* */ /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ /* */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] staging: rtl8723bs: checkpatch - remove mixed spaces/hard-tabs 2017-05-12 1:45 [PATCH 0/4] staging: rtl8723bs: resolve checkpatch issues Matthew Giassa 2017-05-12 1:45 ` [PATCH 1/4] staging: rtl8723bs: checkpatch - remove multiple blank lines Matthew Giassa @ 2017-05-12 1:45 ` Matthew Giassa 2017-05-12 1:45 ` [PATCH 3/4] staging: rtl8723bs: checkpatch - fix typos in comments Matthew Giassa 2017-05-12 1:45 ` [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width Matthew Giassa 3 siblings, 0 replies; 10+ messages in thread From: Matthew Giassa @ 2017-05-12 1:45 UTC (permalink / raw) To: gregkh; +Cc: hdegoede, devel, linux-kernel, matthew Resolving checkpatch issue: WARNING: please, no space before tabs All instances resolved. --- drivers/staging/rtl8723bs/include/rtl8723b_spec.h | 30 +++++++++++------------ 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h index 960d8e4..1f275a7 100644 --- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h +++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h @@ -21,7 +21,7 @@ /* */ /* */ -/* 0x0000h ~ 0x00FFh System Configuration */ +/* 0x0000h ~ 0x00FFh System Configuration */ /* */ /* */ #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ @@ -41,7 +41,7 @@ /* */ /* */ -/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ #define REG_C2HEVT_CMD_ID_8723B 0x01A0 @@ -57,13 +57,13 @@ /* */ /* */ -/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* */ /* */ -/* 0x0280h ~ 0x02FFh RXDMA Configuration */ +/* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ @@ -71,7 +71,7 @@ /* */ /* */ -/* 0x0300h ~ 0x03FFh PCIe */ +/* 0x0300h ~ 0x03FFh PCIe */ /* */ /* */ #define REG_PCIE_CTRL_REG_8723B 0x0300 @@ -98,7 +98,7 @@ /* */ /* */ -/* 0x0400h ~ 0x047Fh Protocol Configuration */ +/* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 @@ -112,14 +112,14 @@ /* */ /* */ -/* 0x0500h ~ 0x05FFh EDCA Configuration */ +/* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 /* */ /* */ -/* 0x0600h ~ 0x07FFh WMAC Configuration */ +/* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ @@ -141,7 +141,7 @@ #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ /* */ -/* 8723 Regsiter Bit and Content definition */ +/* 8723 Regsiter Bit and Content definition */ /* */ /* 2 HSISR */ @@ -154,19 +154,19 @@ /* */ /* */ -/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ /* */ /* */ -/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* */ /* */ -/* 0x0280h ~ 0x02FFh RXDMA Configuration */ +/* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define BIT_USB_RXDMA_AGG_EN BIT(31) @@ -180,7 +180,7 @@ /* */ /* */ -/* 0x0400h ~ 0x047Fh Protocol Configuration */ +/* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ @@ -191,13 +191,13 @@ /* */ /* */ -/* 0x0500h ~ 0x05FFh EDCA Configuration */ +/* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ /* */ /* */ -/* 0x0600h ~ 0x07FFh WMAC Configuration */ +/* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ #define EEPROM_RF_GAIN_OFFSET 0xC1 -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] staging: rtl8723bs: checkpatch - fix typos in comments 2017-05-12 1:45 [PATCH 0/4] staging: rtl8723bs: resolve checkpatch issues Matthew Giassa 2017-05-12 1:45 ` [PATCH 1/4] staging: rtl8723bs: checkpatch - remove multiple blank lines Matthew Giassa 2017-05-12 1:45 ` [PATCH 2/4] staging: rtl8723bs: checkpatch - remove mixed spaces/hard-tabs Matthew Giassa @ 2017-05-12 1:45 ` Matthew Giassa 2017-05-12 1:45 ` [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width Matthew Giassa 3 siblings, 0 replies; 10+ messages in thread From: Matthew Giassa @ 2017-05-12 1:45 UTC (permalink / raw) To: gregkh; +Cc: hdegoede, devel, linux-kernel, matthew Resolving checkpatch issue: CHECK: 'Regsiter' may be misspelled - perhaps 'Register'? CHECK: 'Interrup' may be misspelled - perhaps 'Interrupt'? All instances resolved. --- drivers/staging/rtl8723bs/include/rtl8723b_spec.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h index 1f275a7..1906ff20 100644 --- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h +++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h @@ -141,7 +141,7 @@ #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ /* */ -/* 8723 Regsiter Bit and Content definition */ +/* 8723 Register Bit and Content definition */ /* */ /* 2 HSISR */ @@ -241,13 +241,13 @@ #define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ #define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ #define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrup 1 */ +#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ #define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width 2017-05-12 1:45 [PATCH 0/4] staging: rtl8723bs: resolve checkpatch issues Matthew Giassa ` (2 preceding siblings ...) 2017-05-12 1:45 ` [PATCH 3/4] staging: rtl8723bs: checkpatch - fix typos in comments Matthew Giassa @ 2017-05-12 1:45 ` Matthew Giassa 2017-05-12 3:53 ` kbuild test robot 2017-05-12 9:30 ` Greg KH 3 siblings, 2 replies; 10+ messages in thread From: Matthew Giassa @ 2017-05-12 1:45 UTC (permalink / raw) To: gregkh; +Cc: hdegoede, devel, linux-kernel, matthew Resolving checkpatch issue: WARNING: line over 80 characters Consolidated indentation so local blocks of macros are column-aligned. Slight slight change to make indentation more readable, assuming a 8-space hard-tab indentation style. --- drivers/staging/rtl8723bs/include/rtl8723b_spec.h | 262 +++++++++++++--------- 1 file changed, 159 insertions(+), 103 deletions(-) diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h index 1906ff20..b8298e9 100644 --- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h +++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h @@ -11,32 +11,32 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - *******************************************************************************/ + ******************************************************************************/ #ifndef __RTL8723B_SPEC_H__ #define __RTL8723B_SPEC_H__ #include <autoconf.h> -#define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ +#define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ /* */ /* */ /* 0x0000h ~ 0x00FFh System Configuration */ /* */ /* */ -#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ +#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ #define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038 -#define REG_HSISR_8723B 0x005c -#define REG_PAD_CTRL1_8723B 0x0064 -#define REG_AFE_CTRL_4_8723B 0x0078 -#define REG_HMEBOX_DBG_0_8723B 0x0088 -#define REG_HMEBOX_DBG_1_8723B 0x008A -#define REG_HMEBOX_DBG_2_8723B 0x008C -#define REG_HMEBOX_DBG_3_8723B 0x008E -#define REG_HIMR0_8723B 0x00B0 -#define REG_HISR0_8723B 0x00B4 -#define REG_HIMR1_8723B 0x00B8 -#define REG_HISR1_8723B 0x00BC +#define REG_HSISR_8723B 0x005c +#define REG_PAD_CTRL1_8723B 0x0064 +#define REG_AFE_CTRL_4_8723B 0x0078 +#define REG_HMEBOX_DBG_0_8723B 0x0088 +#define REG_HMEBOX_DBG_1_8723B 0x008A +#define REG_HMEBOX_DBG_2_8723B 0x008C +#define REG_HMEBOX_DBG_3_8723B 0x008E +#define REG_HIMR0_8723B 0x00B0 +#define REG_HISR0_8723B 0x00B4 +#define REG_HIMR1_8723B 0x00B8 +#define REG_HISR1_8723B 0x00BC #define REG_PMC_DBG_CTRL2_8723B 0x00CC /* */ @@ -44,16 +44,16 @@ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ -#define REG_C2HEVT_CMD_ID_8723B 0x01A0 +#define REG_C2HEVT_CMD_ID_8723B 0x01A0 #define REG_C2HEVT_CMD_LEN_8723B 0x01AE -#define REG_WOWLAN_WAKE_REASON 0x01C7 -#define REG_WOWLAN_GTK_DBG1 0x630 -#define REG_WOWLAN_GTK_DBG2 0x634 +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#define REG_WOWLAN_GTK_DBG1 0x630 +#define REG_WOWLAN_GTK_DBG2 0x634 -#define REG_HMEBOX_EXT0_8723B 0x01F0 -#define REG_HMEBOX_EXT1_8723B 0x01F4 -#define REG_HMEBOX_EXT2_8723B 0x01F8 -#define REG_HMEBOX_EXT3_8723B 0x01FC +#define REG_HMEBOX_EXT0_8723B 0x01F0 +#define REG_HMEBOX_EXT1_8723B 0x01F4 +#define REG_HMEBOX_EXT2_8723B 0x01F8 +#define REG_HMEBOX_EXT3_8723B 0x01FC /* */ /* */ @@ -66,8 +66,8 @@ /* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ -#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ -#define REG_RXDMA_MODE_CTRL_8723B 0x0290 +#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ +#define REG_RXDMA_MODE_CTRL_8723B 0x0290 /* */ /* */ @@ -75,25 +75,40 @@ /* */ /* */ #define REG_PCIE_CTRL_REG_8723B 0x0300 -#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ -#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ -#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ -#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ -#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ -#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ -#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ -#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ -#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ -#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ -#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ -#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ +#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address + */ +#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor + * Address + */ +#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor + * Address + */ +#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor + * Address + */ +#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor + * Address + */ +#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor + * Address + */ +#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor + * Address + */ +#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor + * Address + */ +#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ +#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ +#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ +#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ +#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ +#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ +#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ +#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ +#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ /* */ @@ -101,14 +116,14 @@ /* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ -#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 +#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D #ifdef CONFIG_WOWLAN -#define REG_TXPKTBUF_IV_LOW 0x0484 -#define REG_TXPKTBUF_IV_HIGH 0x0488 +#define REG_TXPKTBUF_IV_LOW 0x0484 +#define REG_TXPKTBUF_IV_HIGH 0x0488 #endif -#define REG_AMPDU_BURST_MODE_8723B 0x04BC +#define REG_AMPDU_BURST_MODE_8723B 0x04BC /* */ /* */ @@ -146,11 +161,11 @@ /* 2 HSISR */ /* interrupt mask which needs to clear */ -#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ - HSISR_SPS_OCP_INT |\ - HSISR_RON_INT |\ - HSISR_PDNINT |\ - HSISR_GPIO9_INT) +#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ + HSISR_SPS_OCP_INT |\ + HSISR_RON_INT |\ + HSISR_PDNINT |\ + HSISR_GPIO9_INT) /* */ /* */ @@ -169,12 +184,12 @@ /* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ -#define BIT_USB_RXDMA_AGG_EN BIT(31) +#define BIT_USB_RXDMA_AGG_EN BIT(31) #define RXDMA_AGG_MODE_EN BIT(1) #ifdef CONFIG_WOWLAN #define RXPKT_RELEASE_POLL BIT(16) -#define RXDMA_IDLE BIT(17) +#define RXDMA_IDLE BIT(17) #define RW_RELEASE_EN BIT(18) #endif @@ -185,7 +200,7 @@ /* */ /* */ -/* 8723B REG_CCK_CHECK (offset 0x454) */ +/* 8723B REG_CCK_CHECK (offset 0x454) */ /* */ #define BIT_BCN_PORT_SEL BIT5 @@ -200,58 +215,99 @@ /* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ -#define EEPROM_RF_GAIN_OFFSET 0xC1 -#define EEPROM_RF_GAIN_VAL 0x1F6 +#define EEPROM_RF_GAIN_OFFSET 0xC1 +#define EEPROM_RF_GAIN_VAL 0x1F6 /* */ -/* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ +/* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ /* */ -#define IMR_DISABLED_8723B 0 +#define IMR_DISABLED_8723B 0 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8723B BIT0 /* Receive DMA OK */ +#define IMR_TIMER2_8723B BIT3 /* Timeout interrupt 2 */ +#define IMR_TIMER1_8723B BIT3 /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8723B BIT2 /* Power Save Time Out + * Interrupt + */ +#define IMR_GTINT4_8723B BIT2 /* When GTIMER4 expires, this + * bit is set to 1 + */ +#define IMR_GTINT3_8723B BIT2 /* When GTIMER3 expires, this + * bit is set to 1 + */ +#define IMR_TXBCN0ERR_8723B BIT2 /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8723B BIT2 /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8723B BIT2 /* TSF Timer BIT32 toggle + * indication interrupt + */ +#define IMR_BCNDMAINT0_8723B BIT2 /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8723B BIT1 /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8723B BIT1 /* HSISR Indicator (HSIMR & + * HSISR is true, this bit is + * set to 1) + */ +#define IMR_BCNDMAINT_E_8723B BIT1 /* Beacon DMA Interrupt + * Extension for Win7 + */ +#define IMR_ATIMEND_8723B BIT1 /* CTWidnow End or ATIM Window + * End + */ +#define IMR_C2HCMD_8723B BIT1 /* CPU to Host Command INT + * Status, Write 1 clear + */ +#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT + * Status, Write 1 clear + */ +#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT + * Status, Write 1 clear + */ +#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ +#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ +#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ +#define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ +#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ +#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ +#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ +#define IMR_ROK_8723B BIT0 /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ -#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ -#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ -#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ -#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ -#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ -#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ -#define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK + * Interrupt 7 + */ +#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK + * Interrupt 6 + */ +#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK + * Interrupt 5 + */ +#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK + * Interrupt 4 + */ +#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK + * Interrupt 3 + */ +#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK + * Interrupt 2 + */ +#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK + * Interrupt 1 + */ +#define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension + * for Win7 + */ +#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt + * Status, write 1 clear. + */ +#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, + * Write 1 clear + */ +#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width 2017-05-12 1:45 ` [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width Matthew Giassa @ 2017-05-12 3:53 ` kbuild test robot 2017-05-12 9:30 ` Greg KH 1 sibling, 0 replies; 10+ messages in thread From: kbuild test robot @ 2017-05-12 3:53 UTC (permalink / raw) To: Matthew Giassa; +Cc: kbuild-all, gregkh, devel, hdegoede, matthew, linux-kernel [-- Attachment #1: Type: text/plain, Size: 27343 bytes --] Hi Matthew, [auto build test WARNING on staging/staging-testing] [also build test WARNING on next-20170511] [cannot apply to v4.11] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Matthew-Giassa/staging-rtl8723bs-checkpatch-remove-multiple-blank-lines/20170512-101234 config: i386-allmodconfig (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:384:0: warning: "IMR_TIMER2_8723B" redefined #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:226:0: note: this is the location of the previous definition #define IMR_TIMER2_8723B BIT3 /* Timeout interrupt 2 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:385:0: warning: "IMR_TIMER1_8723B" redefined #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:227:0: note: this is the location of the previous definition #define IMR_TIMER1_8723B BIT3 /* Timeout interrupt 1 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:386:0: warning: "IMR_PSTIMEOUT_8723B" redefined #define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:228:0: note: this is the location of the previous definition #define IMR_PSTIMEOUT_8723B BIT2 /* Power Save Time Out In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:387:0: warning: "IMR_GTINT4_8723B" redefined #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:231:0: note: this is the location of the previous definition #define IMR_GTINT4_8723B BIT2 /* When GTIMER4 expires, this In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:388:0: warning: "IMR_GTINT3_8723B" redefined #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:234:0: note: this is the location of the previous definition #define IMR_GTINT3_8723B BIT2 /* When GTIMER3 expires, this In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:389:0: warning: "IMR_TXBCN0ERR_8723B" redefined #define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:237:0: note: this is the location of the previous definition #define IMR_TXBCN0ERR_8723B BIT2 /* Transmit Beacon0 Error */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:390:0: warning: "IMR_TXBCN0OK_8723B" redefined #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:238:0: note: this is the location of the previous definition #define IMR_TXBCN0OK_8723B BIT2 /* Transmit Beacon0 OK */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:391:0: warning: "IMR_TSF_BIT32_TOGGLE_8723B" redefined #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:239:0: note: this is the location of the previous definition #define IMR_TSF_BIT32_TOGGLE_8723B BIT2 /* TSF Timer BIT32 toggle In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:392:0: warning: "IMR_BCNDMAINT0_8723B" redefined #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:242:0: note: this is the location of the previous definition #define IMR_BCNDMAINT0_8723B BIT2 /* Beacon DMA Interrupt 0 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:393:0: warning: "IMR_BCNDERR0_8723B" redefined #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:243:0: note: this is the location of the previous definition #define IMR_BCNDERR0_8723B BIT1 /* Beacon Queue DMA OK0 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:394:0: warning: "IMR_HSISR_IND_ON_INT_8723B" redefined #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:244:0: note: this is the location of the previous definition #define IMR_HSISR_IND_ON_INT_8723B BIT1 /* HSISR Indicator (HSIMR & In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:395:0: warning: "IMR_BCNDMAINT_E_8723B" redefined #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:248:0: note: this is the location of the previous definition #define IMR_BCNDMAINT_E_8723B BIT1 /* Beacon DMA Interrupt In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:396:0: warning: "IMR_ATIMEND_8723B" redefined #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:251:0: note: this is the location of the previous definition #define IMR_ATIMEND_8723B BIT1 /* CTWidnow End or ATIM Window In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: >> drivers/staging/rtl8723bs/hal/Hal8723BReg.h:397:0: warning: "IMR_C2HCMD_8723B" redefined #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/odm_precomp.h:50, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/core/rtw_efuse.c:19: drivers/staging/rtl8723bs/include/rtl8723b_spec.h:254:0: note: this is the location of the previous definition #define IMR_C2HCMD_8723B BIT1 /* CPU to Host Command INT -- In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:226:0: warning: "IMR_TIMER2_8723B" redefined #define IMR_TIMER2_8723B BIT3 /* Timeout interrupt 2 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:384:0: note: this is the location of the previous definition #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:227:0: warning: "IMR_TIMER1_8723B" redefined #define IMR_TIMER1_8723B BIT3 /* Timeout interrupt 1 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:385:0: note: this is the location of the previous definition #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:228:0: warning: "IMR_PSTIMEOUT_8723B" redefined #define IMR_PSTIMEOUT_8723B BIT2 /* Power Save Time Out In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:386:0: note: this is the location of the previous definition #define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:231:0: warning: "IMR_GTINT4_8723B" redefined #define IMR_GTINT4_8723B BIT2 /* When GTIMER4 expires, this In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:387:0: note: this is the location of the previous definition #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:234:0: warning: "IMR_GTINT3_8723B" redefined #define IMR_GTINT3_8723B BIT2 /* When GTIMER3 expires, this In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:388:0: note: this is the location of the previous definition #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:237:0: warning: "IMR_TXBCN0ERR_8723B" redefined #define IMR_TXBCN0ERR_8723B BIT2 /* Transmit Beacon0 Error */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:389:0: note: this is the location of the previous definition #define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:238:0: warning: "IMR_TXBCN0OK_8723B" redefined #define IMR_TXBCN0OK_8723B BIT2 /* Transmit Beacon0 OK */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:390:0: note: this is the location of the previous definition #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:239:0: warning: "IMR_TSF_BIT32_TOGGLE_8723B" redefined #define IMR_TSF_BIT32_TOGGLE_8723B BIT2 /* TSF Timer BIT32 toggle In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:391:0: note: this is the location of the previous definition #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:242:0: warning: "IMR_BCNDMAINT0_8723B" redefined #define IMR_BCNDMAINT0_8723B BIT2 /* Beacon DMA Interrupt 0 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:392:0: note: this is the location of the previous definition #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:243:0: warning: "IMR_BCNDERR0_8723B" redefined #define IMR_BCNDERR0_8723B BIT1 /* Beacon Queue DMA OK0 */ In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:393:0: note: this is the location of the previous definition #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:244:0: warning: "IMR_HSISR_IND_ON_INT_8723B" redefined #define IMR_HSISR_IND_ON_INT_8723B BIT1 /* HSISR Indicator (HSIMR & In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:394:0: note: this is the location of the previous definition #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:248:0: warning: "IMR_BCNDMAINT_E_8723B" redefined #define IMR_BCNDMAINT_E_8723B BIT1 /* Beacon DMA Interrupt In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:395:0: note: this is the location of the previous definition #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:251:0: warning: "IMR_ATIMEND_8723B" redefined #define IMR_ATIMEND_8723B BIT1 /* CTWidnow End or ATIM Window In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:396:0: note: this is the location of the previous definition #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ In file included from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:20:0, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: >> drivers/staging/rtl8723bs/include/rtl8723b_spec.h:254:0: warning: "IMR_C2HCMD_8723B" redefined #define IMR_C2HCMD_8723B BIT1 /* CPU to Host Command INT In file included from drivers/staging/rtl8723bs/hal/odm_precomp.h:56:0, from drivers/staging/rtl8723bs/include/hal_data.h:18, from drivers/staging/rtl8723bs/include/rtl8723b_hal.h:18, from drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c:19: drivers/staging/rtl8723bs/hal/Hal8723BReg.h:397:0: note: this is the location of the previous definition #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ vim +/IMR_TIMER2_8723B +384 drivers/staging/rtl8723bs/hal/Hal8723BReg.h 554c0a3a Hans de Goede 2017-03-29 378 #define CAMDBG_8723B REG_CAMDBG_8723B 554c0a3a Hans de Goede 2017-03-29 379 #define SECR_8723B REG_SECCFG_8723B /* Security Configuration Register */ 554c0a3a Hans de Goede 2017-03-29 380 554c0a3a Hans de Goede 2017-03-29 381 /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ 554c0a3a Hans de Goede 2017-03-29 382 #define IMR_DISABLED_8723B 0 554c0a3a Hans de Goede 2017-03-29 383 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 554c0a3a Hans de Goede 2017-03-29 @384 #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ 554c0a3a Hans de Goede 2017-03-29 @385 #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ 554c0a3a Hans de Goede 2017-03-29 @386 #define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ 554c0a3a Hans de Goede 2017-03-29 @387 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 554c0a3a Hans de Goede 2017-03-29 @388 #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 554c0a3a Hans de Goede 2017-03-29 @389 #define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ 554c0a3a Hans de Goede 2017-03-29 @390 #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ 554c0a3a Hans de Goede 2017-03-29 @391 #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 554c0a3a Hans de Goede 2017-03-29 @392 #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ 554c0a3a Hans de Goede 2017-03-29 @393 #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ 554c0a3a Hans de Goede 2017-03-29 @394 #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 554c0a3a Hans de Goede 2017-03-29 @395 #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 554c0a3a Hans de Goede 2017-03-29 @396 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ 554c0a3a Hans de Goede 2017-03-29 @397 #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 554c0a3a Hans de Goede 2017-03-29 398 #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 554c0a3a Hans de Goede 2017-03-29 399 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 554c0a3a Hans de Goede 2017-03-29 400 #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ :::::: The code at line 384 was first introduced by commit :::::: 554c0a3abf216c991c5ebddcdb2c08689ecd290b staging: Add rtl8723bs sdio wifi driver :::::: TO: Hans de Goede <hdegoede@redhat.com> :::::: CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 60131 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width 2017-05-12 1:45 ` [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width Matthew Giassa 2017-05-12 3:53 ` kbuild test robot @ 2017-05-12 9:30 ` Greg KH 2017-05-12 12:57 ` Matthew Giassa 1 sibling, 1 reply; 10+ messages in thread From: Greg KH @ 2017-05-12 9:30 UTC (permalink / raw) To: Matthew Giassa; +Cc: hdegoede, devel, linux-kernel On Thu, May 11, 2017 at 06:45:24PM -0700, Matthew Giassa wrote: > +#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ > +#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address > + */ > +#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor > + * Address > + */ Ick, that looks worse to me now, doesn't it to you? Please leave the original as-is. Also, always test-build your patches :) thanks, greg k-h ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width 2017-05-12 9:30 ` Greg KH @ 2017-05-12 12:57 ` Matthew Giassa 2017-05-12 13:24 ` Matthew Giassa 0 siblings, 1 reply; 10+ messages in thread From: Matthew Giassa @ 2017-05-12 12:57 UTC (permalink / raw) To: Greg KH; +Cc: hdegoede, devel, linux-kernel * Greg KH <gregkh@linuxfoundation.org> [2017-05-12 11:30:08 +0200]: >On Thu, May 11, 2017 at 06:45:24PM -0700, Matthew Giassa wrote: >> +#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ >> +#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address >> + */ >> +#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor >> + * Address >> + */ > >Ick, that looks worse to me now, doesn't it to you? Please leave the >original as-is. Will do. >Also, always test-build your patches :) Strange. That built fine on my Ubuntu x64 system: &> make -j2 drivers/staging/rtl8723bs/ ... CC arch/x86/kernel/asm-offsets.s GEN scripts/gdb/linux/constants.py CHK include/generated/asm-offsets.h UPD include/generated/asm-offsets.h CALL scripts/checksyscalls.sh LD drivers/staging/rtl8723bs/built-in.o $> gcc --version gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 >thanks, > >greg k-h Cheers! -- Matthew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width 2017-05-12 12:57 ` Matthew Giassa @ 2017-05-12 13:24 ` Matthew Giassa 2017-05-12 13:54 ` Greg KH 0 siblings, 1 reply; 10+ messages in thread From: Matthew Giassa @ 2017-05-12 13:24 UTC (permalink / raw) To: Greg KH; +Cc: linux-kernel * Matthew Giassa <matthew@giassa.net> [2017-05-12 05:57:44 -0700]: >* Greg KH <gregkh@linuxfoundation.org> [2017-05-12 11:30:08 +0200]: > >>On Thu, May 11, 2017 at 06:45:24PM -0700, Matthew Giassa wrote: >>>+#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ >>>+#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address >>>+ */ >>>+#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor >>>+ * Address >>>+ */ >> >>Ick, that looks worse to me now, doesn't it to you? Please leave the >>original as-is. Paring down CC list to reduce noise for off-topic question. Quick question: in the trivial case, such as a simple block comment, the style guide (process/coding-style.rst) proposes this style: /* * Some comments that span over several lines until column limit. * More comments that span over several lines until column limit. */ Though I see a similar variant often used, which I use by default: /* Some comments that span over several lines until column limit. * More comments that span over several lines until column limit. */ For cases with code plus trailing (lengthy) comment, is it preferred to let it go past the 80 column limit, or to use one of the following multi-line styles? ie: Type I: #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor * Address */ Type II (Ugly): #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor * Address */ Finally, would it be worth proposing the addition of this minor exception to the style guide? Thank you. -- Matthew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width 2017-05-12 13:24 ` Matthew Giassa @ 2017-05-12 13:54 ` Greg KH 0 siblings, 0 replies; 10+ messages in thread From: Greg KH @ 2017-05-12 13:54 UTC (permalink / raw) To: Matthew Giassa; +Cc: linux-kernel On Fri, May 12, 2017 at 06:24:34AM -0700, Matthew Giassa wrote: > * Matthew Giassa <matthew@giassa.net> [2017-05-12 05:57:44 -0700]: > > > * Greg KH <gregkh@linuxfoundation.org> [2017-05-12 11:30:08 +0200]: > > > > > On Thu, May 11, 2017 at 06:45:24PM -0700, Matthew Giassa wrote: > > > > +#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ > > > > +#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address > > > > + */ > > > > +#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor > > > > + * Address > > > > + */ > > > > > > Ick, that looks worse to me now, doesn't it to you? Please leave the > > > original as-is. > > Paring down CC list to reduce noise for off-topic question. > > Quick question: in the trivial case, such as a simple block comment, the > style guide (process/coding-style.rst) proposes this style: > > /* > * Some comments that span over several lines until column limit. > * More comments that span over several lines until column limit. > */ > > Though I see a similar variant often used, which I use by default: > > /* Some comments that span over several lines until column limit. > * More comments that span over several lines until column limit. > */ > > For cases with code plus trailing (lengthy) comment, is it preferred to > let it go past the 80 column limit, or to use one of the following > multi-line styles? ie: > > Type I: > #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor > * Address */ > > Type II (Ugly): > #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor > * Address > */ > Neither, best is: /* TX Beacon Descriptor Address */ #define REG_BCNQ_DESA_8723B 0x0308 > Finally, would it be worth proposing the addition of this minor > exception to the style guide? Not really, it's almost too long as it is today. thanks, greg k-h ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-05-12 13:54 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-05-12 1:45 [PATCH 0/4] staging: rtl8723bs: resolve checkpatch issues Matthew Giassa 2017-05-12 1:45 ` [PATCH 1/4] staging: rtl8723bs: checkpatch - remove multiple blank lines Matthew Giassa 2017-05-12 1:45 ` [PATCH 2/4] staging: rtl8723bs: checkpatch - remove mixed spaces/hard-tabs Matthew Giassa 2017-05-12 1:45 ` [PATCH 3/4] staging: rtl8723bs: checkpatch - fix typos in comments Matthew Giassa 2017-05-12 1:45 ` [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width Matthew Giassa 2017-05-12 3:53 ` kbuild test robot 2017-05-12 9:30 ` Greg KH 2017-05-12 12:57 ` Matthew Giassa 2017-05-12 13:24 ` Matthew Giassa 2017-05-12 13:54 ` Greg KH
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