From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759059AbdEWArw (ORCPT ); Mon, 22 May 2017 20:47:52 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:36048 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964841AbdEWAnE (ORCPT ); Mon, 22 May 2017 20:43:04 -0400 From: Palmer Dabbelt To: linux-kernel@vger.kernel.org To: Arnd Bergmann To: olof@lixom.net Cc: albert@sifive.com Cc: Palmer Dabbelt Subject: [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64} Date: Mon, 22 May 2017 17:41:01 -0700 Message-Id: <20170523004107.536-2-palmer@dabbelt.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170523004107.536-1-palmer@dabbelt.com> References: <20170523004107.536-1-palmer@dabbelt.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RISC-V has both 32-bit and 64-bit base ISAs, but they are very similar. Like some other platforms, we'd like to share one arch directory between the two of them. --- Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Makefile b/Makefile index 63e10bd4f14a..0606f28cd4fd 100644 --- a/Makefile +++ b/Makefile @@ -269,6 +269,14 @@ ifeq ($(ARCH),x86_64) SRCARCH := x86 endif +# Additional ARCH settings for RISC-V +ifeq ($(ARCH),riscv32) + SRCARCH := riscv +endif +ifeq ($(ARCH),riscv64) + SRCARCH := riscv +endif + # Additional ARCH settings for sparc ifeq ($(ARCH),sparc32) SRCARCH := sparc -- 2.13.0