From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751431AbdFEFhq (ORCPT ); Mon, 5 Jun 2017 01:37:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:34338 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751416AbdFEFho (ORCPT ); Mon, 5 Jun 2017 01:37:44 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C182C23A06 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=shawnguo@kernel.org Date: Mon, 5 Jun 2017 13:37:23 +0800 From: Shawn Guo To: Leonard Crestez Cc: Peter Chen , Anson Huang , linux-kernel@vger.kernel.org, Fabio Estevam , linux-arm-kernel@lists.infradead.org, Lucas Stach Subject: Re: [PATCH] ARM: imx6ull: Make suspend/resume work like on 6ul Message-ID: <20170605053722.GI4094@dragon> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 30, 2017 at 07:11:19PM +0300, Leonard Crestez wrote: > Suspend and resume on imx6ull is currenty not working because of some > missed checks where behavior should match imx6ul. > > Signed-off-by: Leonard Crestez > --- > arch/arm/mach-imx/mxc.h | 6 ++++++ > arch/arm/mach-imx/pm-imx6.c | 6 ++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h > index 34f2ff6..e00d626 100644 > --- a/arch/arm/mach-imx/mxc.h > +++ b/arch/arm/mach-imx/mxc.h > @@ -39,6 +39,7 @@ > #define MXC_CPU_IMX6SX 0x62 > #define MXC_CPU_IMX6Q 0x63 > #define MXC_CPU_IMX6UL 0x64 > +#define MXC_CPU_IMX6ULL 0x65 Since you are adding a new CPU type, you should probably patch imx_soc_device_init() for it as well. Shawn > #define MXC_CPU_IMX7D 0x72 > > #define IMX_DDR_TYPE_LPDDR2 1 > @@ -73,6 +74,11 @@ static inline bool cpu_is_imx6ul(void) > return __mxc_cpu_type == MXC_CPU_IMX6UL; > } > > +static inline bool cpu_is_imx6ull(void) > +{ > + return __mxc_cpu_type == MXC_CPU_IMX6ULL; > +} > + > static inline bool cpu_is_imx6q(void) > { > return __mxc_cpu_type == MXC_CPU_IMX6Q; > diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c > index e61b1d1..ecdf071 100644 > --- a/arch/arm/mach-imx/pm-imx6.c > +++ b/arch/arm/mach-imx/pm-imx6.c > @@ -295,7 +295,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) > val &= ~BM_CLPCR_SBYOS; > if (cpu_is_imx6sl()) > val |= BM_CLPCR_BYPASS_PMIC_READY; > - if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) > + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || > + cpu_is_imx6ull()) > val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; > else > val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; > @@ -312,7 +313,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) > val |= BM_CLPCR_SBYOS; > if (cpu_is_imx6sl() || cpu_is_imx6sx()) > val |= BM_CLPCR_BYPASS_PMIC_READY; > - if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) > + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || > + cpu_is_imx6ull()) > val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; > else > val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel