From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751539AbdFEM53 (ORCPT ); Mon, 5 Jun 2017 08:57:29 -0400 Received: from mga05.intel.com ([192.55.52.43]:48157 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751349AbdFEM5Y (ORCPT ); Mon, 5 Jun 2017 08:57:24 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,300,1493708400"; d="scan'208";a="1156705890" From: Mika Westerberg To: Linus Walleij Cc: Heikki Krogerus , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Westerberg Subject: [PATCH 0/3] pinctrl: Add support for Intel Cannon Lake PCH Date: Mon, 5 Jun 2017 15:56:47 +0300 Message-Id: <20170605125650.64188-1-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This series adds support for the pinctrl and GPIO hardware found on the next generation Intel Cannon Lake CPUs. We also update the Intel core pinctrl driver with a concept of hardware pad groups that are needed by the new driver and make it possible to specify mode per pin instead of the whole group. Mika Westerberg (3): pinctrl: intel: Add support for variable size pad groups pinctrl: intel: Make it possible to specify mode per pin in a group pinctrl: intel: Add Intel Cannon Lake PCH pin controller support drivers/pinctrl/intel/Kconfig | 8 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-cannonlake.c | 442 +++++++++++++++++++++++++++ drivers/pinctrl/intel/pinctrl-intel.c | 195 ++++++++---- drivers/pinctrl/intel/pinctrl-intel.h | 64 +++- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 1 + 6 files changed, 647 insertions(+), 64 deletions(-) create mode 100644 drivers/pinctrl/intel/pinctrl-cannonlake.c -- 2.11.0