From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751733AbdFIKAT (ORCPT ); Fri, 9 Jun 2017 06:00:19 -0400 Received: from foss.arm.com ([217.140.101.70]:35860 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751711AbdFIKAR (ORCPT ); Fri, 9 Jun 2017 06:00:17 -0400 Date: Fri, 9 Jun 2017 11:00:14 +0100 From: Will Deacon To: Geetha sowjanya Cc: robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, robert.moore@intel.com, lv.zheng@intel.com, rjw@rjwysocki.net, jcm@redhat.com, linux-kernel@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, devel@acpica.org, linu.cherian@cavium.com, Charles.Garcia-Tobin@arm.com, robh@kernel.org, Geetha Sowjanya Subject: Re: [PATCH v7 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 Message-ID: <20170609100014.GB13955@arm.com> References: <1496145821-3411-1-git-send-email-gakula@caviumnetworks.com> <1496145821-3411-4-git-send-email-gakula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1496145821-3411-4-git-send-email-gakula@caviumnetworks.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geetha, On Tue, May 30, 2017 at 05:33:41PM +0530, Geetha sowjanya wrote: > From: Geetha Sowjanya > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > lines for gerror, eventq and cmdq-sync. > > This patch addresses the issue by checking if any interrupt sources are > using same irq number, then they are registered as shared irqs. > > Signed-off-by: Geetha Sowjanya > --- > Documentation/arm64/silicon-errata.txt | 1 + > drivers/iommu/arm-smmu-v3.c | 29 +++++++++++++++++++++++++---- > 2 files changed, 26 insertions(+), 4 deletions(-) > > diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt > index 4693a32..42422f6 100644 > --- a/Documentation/arm64/silicon-errata.txt > +++ b/Documentation/arm64/silicon-errata.txt > @@ -63,6 +63,7 @@ stable kernels. > | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | > | Cavium | ThunderX SMMUv2 | #27704 | N/A | > | Cavium | ThunderX2 SMMUv3| #74 | N/A | > +| Cavium | ThunderX2 SMMUv3| #126 | N/A | > | | | | | > | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | > | | | | | > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index 4e80205..d2db01f 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -2232,6 +2232,25 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) > devm_add_action(dev, arm_smmu_free_msis, dev); > } > > +static int get_irq_flags(struct arm_smmu_device *smmu, int irq) > +{ > + int match_count = 0; > + > + if (irq == smmu->evtq.q.irq) > + match_count++; > + if (irq == smmu->cmdq.q.irq) > + match_count++; > + if (irq == smmu->gerr_irq) > + match_count++; > + if (irq == smmu->priq.q.irq) > + match_count++; > + > + if (match_count > 1) > + return IRQF_SHARED | IRQF_ONESHOT; > + > + return IRQF_ONESHOT; > +} I really think this is the wrong way of solving the problem: using IRQF_SHARED has implications elsewhere in the driver (for example, we must then pass a unique dev_id otherwise freeing the IRQs won't work properly) and I don't want to have to worry about these constraints just because of this broken platform. Please do what I suggested instead: register a single threaded interrupt handler that acts as a multiplexer and manually calls the other routines. Will