From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754696AbdFNIaY (ORCPT ); Wed, 14 Jun 2017 04:30:24 -0400 Received: from mga04.intel.com ([192.55.52.120]:27103 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754175AbdFNIaU (ORCPT ); Wed, 14 Jun 2017 04:30:20 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,340,1493708400"; d="scan'208";a="1141129210" Date: Wed, 14 Jun 2017 14:02:52 +0530 From: Vinod Koul To: Icenowy Zheng Cc: Maxime Ripard , Chen-Yu Tsai , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: Re: [PATCH 1/2] dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk Message-ID: <20170614083252.GK13020@localhost> References: <20170605123348.26137-1-icenowy@aosc.io> <20170605123348.26137-2-icenowy@aosc.io> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170605123348.26137-2-icenowy@aosc.io> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 05, 2017 at 08:33:47PM +0800, Icenowy Zheng wrote: > From: Icenowy Zheng > > Originally we enable a special gate bit when the compatible indicates > A23/33. > > But according to BSP sources and user manuals, more SoCs will need this > gate bit. > > So make it a common quirk configured in the config struct. > > Signed-off-by: Icenowy Zheng > --- > Changes since original codec patchset v3: > - Refactored comments to cover some words found in official documents. > - Removed the comments when toggling the gate bit. > > drivers/dma/sun6i-dma.c | 20 +++++++++++++------- > 1 file changed, 13 insertions(+), 7 deletions(-) > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c > index a2358780ab2c..252b59c1d1d5 100644 > --- a/drivers/dma/sun6i-dma.c > +++ b/drivers/dma/sun6i-dma.c > @@ -101,6 +101,17 @@ struct sun6i_dma_config { > u32 nr_max_channels; > u32 nr_max_requests; > u32 nr_max_vchans; > + /* > + * In the datasheets/user manuals of newer Allwinner SoCs, a special > + * bit (bit 2 at register 0x20) is present. > + * It's named "DMA MCLK interface circuit auto gating bit" in the > + * documents, and the footnote of this register says that this bit > + * should be set up when initializing the DMA controller. > + * Allwinner A23/A33 user manuals do not have this bit documented, > + * however these SoCs really have and need this bit, as seen in the > + * BSP kernel source code. > + */ > + bool gate_needed; Since this is a hw property, why is this not added as an optional DT property? > }; > > /* > @@ -1009,6 +1020,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { > .nr_max_channels = 8, > .nr_max_requests = 24, > .nr_max_vchans = 37, > + .gate_needed = true, > }; > > static struct sun6i_dma_config sun8i_a83t_dma_cfg = { > @@ -1174,13 +1186,7 @@ static int sun6i_dma_probe(struct platform_device *pdev) > goto err_dma_unregister; > } > > - /* > - * sun8i variant requires us to toggle a dma gating register, > - * as seen in Allwinner's SDK. This register is not documented > - * in the A23 user manual. > - */ > - if (of_device_is_compatible(pdev->dev.of_node, > - "allwinner,sun8i-a23-dma")) > + if (sdc->cfg->gate_needed) > writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE); > > return 0; > -- > 2.12.2 > -- ~Vinod