From: Will Deacon <will.deacon@arm.com>
To: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: linux-kernel@vger.kernel.org, ldr709@gmail.com,
dhowells@redhat.com, peterz@infradead.org, corbet@lwn.net,
stern@rowland.harvard.edu, parri.andrea@gmail.com,
j.alglave@ucl.ac.uk, luc.maranget@inria.fr
Subject: Re: [PATCH] doc: Update memory-barriers.txt for read-to-write dependencies
Date: Wed, 5 Jul 2017 10:46:45 +0100 [thread overview]
Message-ID: <20170705094645.GC10112@arm.com> (raw)
In-Reply-To: <20170704214651.GP2393@linux.vnet.ibm.com>
On Tue, Jul 04, 2017 at 02:46:51PM -0700, Paul E. McKenney wrote:
> On Tue, Jul 04, 2017 at 05:36:36PM +0100, Will Deacon wrote:
> > On Mon, Jul 03, 2017 at 10:41:06AM -0700, Paul E. McKenney wrote:
> > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> > > index 9d5e0f853f08..7be80911e502 100644
> > > --- a/Documentation/memory-barriers.txt
> > > +++ b/Documentation/memory-barriers.txt
> > > @@ -594,7 +594,23 @@ between the address load and the data load:
> > > This enforces the occurrence of one of the two implications, and prevents the
> > > third possibility from arising.
> > >
> > > -A data-dependency barrier must also order against dependent writes:
> > > +
> > > +[!] Note that this extremely counterintuitive situation arises most easily on
> > > +machines with split caches, so that, for example, one cache bank processes
> > > +even-numbered cache lines and the other bank processes odd-numbered cache
> > > +lines. The pointer P might be stored in an odd-numbered cache line, and the
> > > +variable B might be stored in an even-numbered cache line. Then, if the
> > > +even-numbered bank of the reading CPU's cache is extremely busy while the
> > > +odd-numbered bank is idle, one can see the new value of the pointer P (&B),
> > > +but the old value of the variable B (2).
> > > +
> > > +
> > > +A data-dependency barrier is not required to order dependent writes
> > > +because the CPUs that the Linux kernel supports don't do writes until
> > > +they are certain (1) that the write will actually happen, (2) of the
> > > +location of the write, and (3) of the value to be written. But please
> > > +carefully read the "CONTROL DEPENDENCIES" section: The compiler can
> > > +and does break control dependencies in a great many situations.
> >
> > This makes it sound like only control dependencies are susceptible to
> > being broken by compiler optimisations, so I'd drop the "control" and
> > just say "The compiler can and does break dependencies in a great many
> > situations".
> >
> > With that:
> >
> > Acked-by: Will Deacon <will.deacon@arm.com>
>
> Done! I also added a pointer to Documentation/RCU/rcu_dereference.txt,
> which lists some of the vandalism^Woptimizations that modern compilers
> can commit. Does the updated patch below capture it?
Yes, thanks Paul.
Will
prev parent reply other threads:[~2017-07-05 9:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-30 23:28 [PATCH] doc: Update memory-barriers.txt for read-to-write dependencies Paul E. McKenney
2017-07-03 13:07 ` Will Deacon
2017-07-03 17:41 ` Paul E. McKenney
2017-07-04 16:36 ` Will Deacon
2017-07-04 21:46 ` Paul E. McKenney
2017-07-05 9:46 ` Will Deacon [this message]
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