From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751340AbdH0L3d (ORCPT ); Sun, 27 Aug 2017 07:29:33 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:38833 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751124AbdH0L3c (ORCPT ); Sun, 27 Aug 2017 07:29:32 -0400 Date: Sun, 27 Aug 2017 14:29:26 +0300 From: Cyrill Gorcunov To: "Kirill A. Shutemov" Cc: Linus Torvalds , x86@kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andrew Morton , Andy Lutomirski , Dmitry Safonov , Borislav Petkov , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCHv5 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Message-ID: <20170827112926.GA1942@uranus.lan> References: <20170821152916.40124-1-kirill.shutemov@linux.intel.com> <20170821152916.40124-7-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170821152916.40124-7-kirill.shutemov@linux.intel.com> User-Agent: Mutt/1.8.3 (2017-05-23) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 21, 2017 at 06:29:03PM +0300, Kirill A. Shutemov wrote: > This patch prepare decompression code to boot-time switching between 4- > and 5-level paging. > > Signed-off-by: Kirill A. Shutemov > --- > arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S > index fbf4c32d0b62..2e362aea3319 100644 > --- a/arch/x86/boot/compressed/head_64.S > +++ b/arch/x86/boot/compressed/head_64.S > @@ -347,6 +347,28 @@ preferred_addr: > leaq boot_stack_end(%rbx), %rsp > > #ifdef CONFIG_X86_5LEVEL > + /* Preserve rbx across cpuid */ > + movq %rbx, %r8 > + > + /* Check if leaf 7 is supported */ > + movl $0, %eax Use xor instead, it should be shorter > + cpuid > + cmpl $7, %eax > + jb lvl5 > + > + /* > + * Check if la57 is supported. > + * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16] > + */ > + movl $7, %eax > + movl $0, %ecx same