From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751525AbdJCR2j (ORCPT ); Tue, 3 Oct 2017 13:28:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50000 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750767AbdJCR2h (ORCPT ); Tue, 3 Oct 2017 13:28:37 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A574E2CE907 Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=rkrcmar@redhat.com Date: Tue, 3 Oct 2017 19:28:34 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Wanpeng Li Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Paolo Bonzini , Wanpeng Li Subject: Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer Message-ID: <20171003172833.GC21107@flask> References: <1506647099-2688-1-git-send-email-wanpeng.li@hotmail.com> <1506647099-2688-4-git-send-email-wanpeng.li@hotmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1506647099-2688-4-git-send-email-wanpeng.li@hotmail.com> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 03 Oct 2017 17:28:37 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-09-28 18:04-0700, Wanpeng Li: > From: Wanpeng Li > > The description in the Intel SDM of how the divide configuration > register is used: "The APIC timer frequency will be the processor's bus > clock or core crystal clock frequency divided by the value specified in > the divide configuration register." > > Observation of baremetal shown that when the TDCR is change, the TMCCT > does not change or make a big jump in value, but the rate at which it > count down change. > > The patch update the emulation to APIC timer to so that a change to the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- Why do we need to do more than just restart the timer? The TMCCT should remain roughly at the same level -- changing divide count modifies target_expiration and it looks like apic_get_tmcct() would get the same result like before changing divide count. Thanks.