From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752122AbdJDMnx (ORCPT ); Wed, 4 Oct 2017 08:43:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60060 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751696AbdJDMnv (ORCPT ); Wed, 4 Oct 2017 08:43:51 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 50AE0820E5 Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=rkrcmar@redhat.com Date: Wed, 4 Oct 2017 14:43:43 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Wanpeng Li Cc: "linux-kernel@vger.kernel.org" , kvm , Paolo Bonzini , Wanpeng Li Subject: Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer Message-ID: <20171004124343.GD20277@flask> References: <1506647099-2688-1-git-send-email-wanpeng.li@hotmail.com> <1506647099-2688-4-git-send-email-wanpeng.li@hotmail.com> <20171003172833.GC21107@flask> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Wed, 04 Oct 2017 12:43:51 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-10-04 09:59+0800, Wanpeng Li: > 2017-10-04 1:28 GMT+08:00 Radim Krčmář : > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> The description in the Intel SDM of how the divide configuration > >> register is used: "The APIC timer frequency will be the processor's bus > >> clock or core crystal clock frequency divided by the value specified in > >> the divide configuration register." > >> > >> Observation of baremetal shown that when the TDCR is change, the TMCCT > >> does not change or make a big jump in value, but the rate at which it > >> count down change. > >> > >> The patch update the emulation to APIC timer to so that a change to the > >> divide configuration would be reflected in the value of the counter and > >> when the next interrupt is triggered. > >> > >> Cc: Paolo Bonzini > >> Cc: Radim Krčmář > >> Signed-off-by: Wanpeng Li > >> --- > > > > Why do we need to do more than just restart the timer? > > Because the current timer (hv or sw) are still running. I think the > goal of this commit is to runtime update the rate of the current timer > which is running. Our restart_apic_timer() implementation just cancels > the current timer when switch between preemption timer and hrtimer. I see ... we do need to know both divisors in order to make it work, thanks.