From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752448AbdJDODG (ORCPT ); Wed, 4 Oct 2017 10:03:06 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23111 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752220AbdJDODF (ORCPT ); Wed, 4 Oct 2017 10:03:05 -0400 Date: Wed, 4 Oct 2017 15:03:02 +0100 From: James Hogan To: Ed Blake CC: , , , Subject: Re: [PATCH 4/4] irqchip: imgpdc: Pass on peripheral mask/unmasks to the parent Message-ID: <20171004140302.GG25320@jhogan-linux.le.imgtec.org> References: <1506938159-466-1-git-send-email-ed.blake@sondrel.com> <1506938159-466-5-git-send-email-ed.blake@sondrel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="32u276st3Jlj2kUU" Content-Disposition: inline In-Reply-To: <1506938159-466-5-git-send-email-ed.blake@sondrel.com> User-Agent: Mutt/1.7.2 (2016-11-26) X-Originating-IP: [192.168.154.110] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --32u276st3Jlj2kUU Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Ed, On Mon, Oct 02, 2017 at 10:55:59AM +0100, Ed Blake wrote: >=20 > Pass on peripheral (RTC/IR/WD) irq masks and unmasks to the parent > interrupt controller, as well as setting / clearing the relevant bits > in the IRQ_ROUTE register. >=20 > Clearing bits in the IRQ_ROUTE register will prevent future interrupts > from being passed on to the parent, but won't mask an existing > interrupt which has already made it to the parent. Is it an edge or level sensitive interrupt from the PDC? I'm a little rusty on the IRQ subsystem TBH, but if edge sensitive I would have expected the parent interrupt to be acked/cleared by the parent handler. And if level sensitive I would have expected the deasserted parent interrupt to be masked by the parent handler, and immediately cleared upon rerouting. Maybe you can clarify whats going on here. Cheers James > This is currently > causing peipheral interrupts to fire continuously when the system wakes > from a suspended state when one of the peripherals is used to wake the > system (e.g. RTC, IR). The interrupt occurs early in the wake process > (still in the noirq phase) and because the peripheral interrupt is > disabled at that point, the core marks it as pending and masks it out. > This mask must be passed to the parent controller to be effective. >=20 > Signed-off-by: Ed Blake > --- > drivers/irqchip/irq-imgpdc.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) >=20 > diff --git a/drivers/irqchip/irq-imgpdc.c b/drivers/irqchip/irq-imgpdc.c > index d1bcfef..05c48dd 100644 > --- a/drivers/irqchip/irq-imgpdc.c > +++ b/drivers/irqchip/irq-imgpdc.c > @@ -141,21 +141,31 @@ static struct pdc_intc_priv *irqd_to_priv(struct ir= q_data *data) > static void perip_irq_mask(struct irq_data *data) > { > struct pdc_intc_priv *priv =3D irqd_to_priv(data); > + unsigned int parent_irq =3D priv->perip_irqs[data->hwirq]; > + struct irq_data *parent_irq_data =3D irq_get_irq_data(parent_irq); > =20 > raw_spin_lock(&priv->lock); > priv->irq_route &=3D ~data->mask; > pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); > raw_spin_unlock(&priv->lock); > + > + /* Pass on the mask to the parent */ > + parent_irq_data->chip->irq_mask(parent_irq_data); > } > =20 > static void perip_irq_unmask(struct irq_data *data) > { > struct pdc_intc_priv *priv =3D irqd_to_priv(data); > + unsigned int parent_irq =3D priv->perip_irqs[data->hwirq]; > + struct irq_data *parent_irq_data =3D irq_get_irq_data(parent_irq); > =20 > raw_spin_lock(&priv->lock); > priv->irq_route |=3D data->mask; > pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); > raw_spin_unlock(&priv->lock); > + > + /* Pass on the unmask to the parent */ > + parent_irq_data->chip->irq_unmask(parent_irq_data); > } > =20 > static int syswake_irq_set_type(struct irq_data *data, unsigned int flow= _type) > --=20 > 1.9.1 >=20 --32u276st3Jlj2kUU Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEd80NauSabkiESfLYbAtpk944dnoFAlnU6hYACgkQbAtpk944 dnrcNg//XqR83NP1Wwzz/bpoMYcODQusvhpll1ebxsyd+o/nhFYWyTMQM6FBrkpB XLM7WiYWNkKPBzEg61dw40lMmjVGi0wZL11awbG6AH8DUHi4QXPBynn+Nw/3k3Xh 4SptNi0w/YxD/coF7pQyvUwL1LVRLTz25AVO5LHKh16OVAmLuyiuXQSfiL9vAb1x V5OpQoV2KXtGtExojbZVrYc7Fic702tGu1BWxWo6lxd7iQRYEJ9TF93zUu5Oz5Kt U43BbZNbB6KrtxwicWXrQbUxEkycd1bar6FmPqKwvI51RxQ0TdGWwIFPu3YCm7z9 sZOqXz0qupaxrsQmZEX2w90OkzZxFdIsCUfVN1thJ5UVG7m+PgMsp4pz37/WTtty qNROofPyO/8c2TJcwCf+GrtSSXEjYWcWLB14BXDH2iLImNqZ03FNNZd7gJX3uIsm IRodmOH5+d8OhZwm6IVWp1ZQxSlLjuh4pLuch/LckbRtfgWRV1c1yzDMbwoA3HzZ I7uQga15oTmrKelU+uTz3N0KnFC4+Uscyrj9T/7hZ1HpoUa0BNgseNN2tjEUON0E VXXbMTHLWHn1wUeeIJPkaICnARw56IrkLXYmj9FXe7R7+SKYW99Z8nYpkJAOVGqN Mh9CpFOw+PkLBhuOghUIpV8PQlg59WM2XfPFDFgdwK4u9UzLx28= =49IM -----END PGP SIGNATURE----- --32u276st3Jlj2kUU--