[PATCH 0/2] MIPS: Minor FPU emulation fixes

[PATCH 0/2] MIPS: Minor FPU emulation fixes

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>

This series contains two minor FPU emulation patches that
were not included into a recent larger series of FPU fixes,
mainly not to additionally burden already complex set of
patches.

Only the first patch changes functionality, and in such way
that it affects certain Mips debugfs features only.

The second one is just a cosmetic change - it just cleans
the code, and removes some checkpatch warnings.

Aleksandar Markovic (2):
  MIPS: math-emu: Update debugfs FP exception stats for certain
    instructions
  MIPS: math-emu: Use preferred flavor of unsigned integer declarations

 arch/mips/math-emu/cp1emu.c     | 46 +++++++++++++++++++++--------------------
 arch/mips/math-emu/dp_maddf.c   |  8 +++----
 arch/mips/math-emu/dp_mul.c     |  8 +++----
 arch/mips/math-emu/dp_sqrt.c    |  4 ++--
 arch/mips/math-emu/ieee754.h    | 15 +++++++-------
 arch/mips/math-emu/ieee754int.h |  6 +++---
 arch/mips/math-emu/ieee754sp.c  |  4 ++--
 arch/mips/math-emu/ieee754sp.h  |  2 +-
 arch/mips/math-emu/sp_div.c     |  4 ++--
 arch/mips/math-emu/sp_fint.c    |  2 +-
 arch/mips/math-emu/sp_maddf.c   |  6 +++---
 arch/mips/math-emu/sp_mul.c     | 10 ++++-----
 12 files changed, 59 insertions(+), 56 deletions(-)

-- 
2.7.4

[PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>

Fix omission of updating of debugfs FP exception stats for
instructions <CLASS|MADDF|MSUBF|MAX|MIN|MAXA|MINA>.<D|S>.

CLASS.<D|S> can generate Unimplemented Operation FP exception.
<MADDF|MSUBF|MAX|MIN|MAXA|MINA>>.<D|S> can generate Inexact,
Unimplemented Operation, Invalid Operation, Overflow, and
Underflow FP exceptions. In such cases, and prior to this
patch, debugfs FP exception stats were not updated, and
therefore contained overall wrong values.

This brings the emulation of mentioned instructions consistent
with the previously implemented emulation of other related
FPU instructions.

There is still some room for refactoring and improving the
code segment under label "copcsr", but this is beyond the
scope of this patch.

Fixes: 38db37ba069f ("MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction")
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Fixes: a79f5f9ba508 ("MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction")
Fixes: 4e9561b20e2f ("MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction")

Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
 arch/mips/math-emu/cp1emu.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 192542d..d2fcb30 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1795,7 +1795,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			SPFROMREG(fd, MIPSInst_FD(ir));
 			rv.s = ieee754sp_maddf(fd, fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmsubf_op: {
@@ -1809,7 +1809,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			SPFROMREG(fd, MIPSInst_FD(ir));
 			rv.s = ieee754sp_msubf(fd, fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case frint_op: {
@@ -1834,7 +1834,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.w = ieee754sp_2008class(fs);
 			rfmt = w_fmt;
-			break;
+			goto copcsr;
 		}
 
 		case fmin_op: {
@@ -1847,7 +1847,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(ft, MIPSInst_FT(ir));
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = ieee754sp_fmin(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmina_op: {
@@ -1860,7 +1860,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(ft, MIPSInst_FT(ir));
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = ieee754sp_fmina(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmax_op: {
@@ -1873,7 +1873,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(ft, MIPSInst_FT(ir));
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = ieee754sp_fmax(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmaxa_op: {
@@ -1886,7 +1886,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			SPFROMREG(ft, MIPSInst_FT(ir));
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = ieee754sp_fmaxa(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fabs_op:
@@ -2165,7 +2165,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			DPFROMREG(fd, MIPSInst_FD(ir));
 			rv.d = ieee754dp_maddf(fd, fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmsubf_op: {
@@ -2179,7 +2179,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			DPFROMREG(fd, MIPSInst_FD(ir));
 			rv.d = ieee754dp_msubf(fd, fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case frint_op: {
@@ -2204,7 +2204,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.l = ieee754dp_2008class(fs);
 			rfmt = l_fmt;
-			break;
+			goto copcsr;
 		}
 
 		case fmin_op: {
@@ -2217,7 +2217,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(ft, MIPSInst_FT(ir));
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = ieee754dp_fmin(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmina_op: {
@@ -2230,7 +2230,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(ft, MIPSInst_FT(ir));
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = ieee754dp_fmina(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmax_op: {
@@ -2243,7 +2243,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(ft, MIPSInst_FT(ir));
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = ieee754dp_fmax(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fmaxa_op: {
@@ -2256,7 +2256,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			DPFROMREG(ft, MIPSInst_FT(ir));
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = ieee754dp_fmaxa(fs, ft);
-			break;
+			goto copcsr;
 		}
 
 		case fabs_op:
-- 
2.7.4

Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 6547 bytes --]

On Fri, Oct 06, 2017 at 07:29:00PM +0200, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> 
> Fix omission of updating of debugfs FP exception stats for
> instructions <CLASS|MADDF|MSUBF|MAX|MIN|MAXA|MINA>.<D|S>.
> 
> CLASS.<D|S> can generate Unimplemented Operation FP exception.
> <MADDF|MSUBF|MAX|MIN|MAXA|MINA>>.<D|S> can generate Inexact,

nit: s/>>/>/

> Unimplemented Operation, Invalid Operation, Overflow, and
> Underflow FP exceptions. In such cases, and prior to this

Well, according to the manual I'm looking at MAX|MIN|MAXA|MINA can't
generate inexact, overflow, or underflow FP exceptions, and in practice
the only FPE generated by emulating these instructions is invalid
operation for MADDF/MSUBF. So presumably that's the only case we really
care about.

I.e. the MADDF/MSUBF invalid operation should be counted, but crucially
the setting of rcsr bits allows it to generate a SIGFPE which from a
glance it doesn't appear to do until this patch. The other changes are
redundant and harmless.

Does that sound correct? (appologies if I'm missing something, I'm just
reading the code, and reading FPU emulation code late at night is
probably asking for trouble).

Given the potential fixing of SIGFPE in that case should this be tagged
for stable?

Thanks
James


> patch, debugfs FP exception stats were not updated, and
> therefore contained overall wrong values.
> 
> This brings the emulation of mentioned instructions consistent
> with the previously implemented emulation of other related
> FPU instructions.
> 
> There is still some room for refactoring and improving the
> code segment under label "copcsr", but this is beyond the
> scope of this patch.
> 
> Fixes: 38db37ba069f ("MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction")
> Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
> Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
> Fixes: a79f5f9ba508 ("MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction")
> Fixes: 4e9561b20e2f ("MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction")
> 
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
>  arch/mips/math-emu/cp1emu.c | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
> index 192542d..d2fcb30 100644
> --- a/arch/mips/math-emu/cp1emu.c
> +++ b/arch/mips/math-emu/cp1emu.c
> @@ -1795,7 +1795,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			SPFROMREG(fd, MIPSInst_FD(ir));
>  			rv.s = ieee754sp_maddf(fd, fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmsubf_op: {
> @@ -1809,7 +1809,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			SPFROMREG(fd, MIPSInst_FD(ir));
>  			rv.s = ieee754sp_msubf(fd, fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case frint_op: {
> @@ -1834,7 +1834,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.w = ieee754sp_2008class(fs);
>  			rfmt = w_fmt;
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmin_op: {
> @@ -1847,7 +1847,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(ft, MIPSInst_FT(ir));
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.s = ieee754sp_fmin(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmina_op: {
> @@ -1860,7 +1860,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(ft, MIPSInst_FT(ir));
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.s = ieee754sp_fmina(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmax_op: {
> @@ -1873,7 +1873,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(ft, MIPSInst_FT(ir));
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.s = ieee754sp_fmax(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmaxa_op: {
> @@ -1886,7 +1886,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			SPFROMREG(ft, MIPSInst_FT(ir));
>  			SPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.s = ieee754sp_fmaxa(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fabs_op:
> @@ -2165,7 +2165,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			DPFROMREG(fd, MIPSInst_FD(ir));
>  			rv.d = ieee754dp_maddf(fd, fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmsubf_op: {
> @@ -2179,7 +2179,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			DPFROMREG(fd, MIPSInst_FD(ir));
>  			rv.d = ieee754dp_msubf(fd, fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case frint_op: {
> @@ -2204,7 +2204,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.l = ieee754dp_2008class(fs);
>  			rfmt = l_fmt;
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmin_op: {
> @@ -2217,7 +2217,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(ft, MIPSInst_FT(ir));
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.d = ieee754dp_fmin(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmina_op: {
> @@ -2230,7 +2230,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(ft, MIPSInst_FT(ir));
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.d = ieee754dp_fmina(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmax_op: {
> @@ -2243,7 +2243,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(ft, MIPSInst_FT(ir));
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.d = ieee754dp_fmax(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fmaxa_op: {
> @@ -2256,7 +2256,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  			DPFROMREG(ft, MIPSInst_FT(ir));
>  			DPFROMREG(fs, MIPSInst_FS(ir));
>  			rv.d = ieee754dp_fmaxa(fs, ft);
> -			break;
> +			goto copcsr;
>  		}
>  
>  		case fabs_op:
> -- 
> 2.7.4
> 

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

RE: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[Aleksandar Markovic]

Thanks, James, for the review.

I've got a couple of points bellow that will, I hope, clarify several issues.

> ________________________________________
> From: James Hogan [james.hogan@mips.com]
> Sent: Monday, October 09, 2017 2:09 PM
> To: Aleksandar Markovic
> Cc: linux-mips@linux-mips.org; Aleksandar Markovic; Douglas Leung;
> Goran Ferenc; linux-kernel@vger.kernel.org; Maciej Rozycki;
> Manuel Lauss; Masahiro Yamada; Miodrag Dinic; Paul Burton;
> Petar Jovanovic; Raghu Gandham; Ralf Baechle
> Subject: Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP
> exception stats for certain instructions
> 
> On Fri, Oct 06, 2017 at 07:29:00PM +0200, Aleksandar Markovic wrote:
> > From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> >
> > Fix omission of updating of debugfs FP exception stats for
> > instructions <CLASS|MADDF|MSUBF|MAX|MIN|MAXA|MINA>.<D|S>.
> >
> > CLASS.<D|S> can generate Unimplemented Operation FP exception.
> > <MADDF|MSUBF|MAX|MIN|MAXA|MINA>>.<D|S> can generate Inexact,
> 
> nit: s/>>/>/

Will be fixed in v2.

> 
> > Unimplemented Operation, Invalid Operation, Overflow, and
> > Underflow FP exceptions. In such cases, and prior to this
> 
> Well, according to the manual I'm looking at MAX|MIN|MAXA|MINA can't
> generate inexact, overflow, or underflow FP exceptions
>

The "MIPS64® Instruction Set Reference Manual" v6.00 mentions that all
five FP exception are possible for MAX|MIN|MAXA|MINA, but in v6.05, the
list was reduced to only two, as you hinted. I am going to sync the commit
message with v6.05 of the document.

> ... and in practice
> the only FPE generated by emulating these instructions is invalid
> operation for MADDF/MSUBF. So presumably that's the only case we really
> care about.
> 
> I.e. the MADDF/MSUBF invalid operation should be counted, but crucially
> the setting of rcsr bits allows it to generate a SIGFPE which from a
> glance it doesn't appear to do until this patch. The other changes are
> redundant and harmless.
> 
> Does that sound correct? (appologies if I'm missing something, I'm just
> reading the code, and reading FPU emulation code late at night is
> probably asking for trouble).
>

You are close, but not quite, I'll explain that in a moment.

First, just to note that SIGFPE will be generated if the condition

((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E)

is met (the code is almost at the end of fpu_emu(), cp1emu.c, line 1557).
ctx is one of the arguments of fpu_emu(), but, in the current state of the
code, by analyzing several levels of invocations, it can be concluded
that ctx will always be equal to &current->thread.fpu. So, the register
current->thread.fpu->fcr31 is actually important here.

Now, let's consider, for simplicity, the case of MADDF operation resulting
in an overflow caused by addition of two large FP numbers. The "special"
treatment of such case will be done within invocation of ieee754dp_format(),
which will in turn (in this particular example) execute
ieee754_setcx(IEEE754_OVERFLOW), which will further execute

	ieee754_csr.cx |= flags;
	ieee754_csr.sx |= flags;

and, since ieee754_csr is macro for &current->thread.fpu.fcr31, this will result
in setting tworelevant and correct bits in current->thread.fpu->fcr31.

This means that condition from few paragraphs above will be met, and SIGFPE
will be generated.

Whole above scenario happens regardless of inclusion of this patch.

Actually, setting exception bits within "copcsr label code" seems redundant.
It though does no harm. I have some theory why is this code here, and why
we even may want to keep it as is, but this would be too much for this mail.

> 
> Given the potential fixing of SIGFPE in that case should this be tagged
> for stable?
> 

As I explained above, SIGFPE behavior is already correct, without this patch.
This patch fixes only debugfs stats. So, it is not that critical.

Looking forward to your response.

Aleksandar

Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 4713 bytes --]

On Wed, Oct 11, 2017 at 04:18:49PM +0000, Aleksandar Markovic wrote:
> Thanks, James, for the review.
> 
> I've got a couple of points bellow that will, I hope, clarify several issues.
> 
> > ________________________________________
> > From: James Hogan [james.hogan@mips.com]
> > Sent: Monday, October 09, 2017 2:09 PM
> > To: Aleksandar Markovic
> > Cc: linux-mips@linux-mips.org; Aleksandar Markovic; Douglas Leung;
> > Goran Ferenc; linux-kernel@vger.kernel.org; Maciej Rozycki;
> > Manuel Lauss; Masahiro Yamada; Miodrag Dinic; Paul Burton;
> > Petar Jovanovic; Raghu Gandham; Ralf Baechle
> > Subject: Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP
> > exception stats for certain instructions
> > 
> > On Fri, Oct 06, 2017 at 07:29:00PM +0200, Aleksandar Markovic wrote:
> > > From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> > >
> > > Fix omission of updating of debugfs FP exception stats for
> > > instructions <CLASS|MADDF|MSUBF|MAX|MIN|MAXA|MINA>.<D|S>.
> > >
> > > CLASS.<D|S> can generate Unimplemented Operation FP exception.
> > > <MADDF|MSUBF|MAX|MIN|MAXA|MINA>>.<D|S> can generate Inexact,
> > 
> > nit: s/>>/>/
> 
> Will be fixed in v2.
> 
> > 
> > > Unimplemented Operation, Invalid Operation, Overflow, and
> > > Underflow FP exceptions. In such cases, and prior to this
> > 
> > Well, according to the manual I'm looking at MAX|MIN|MAXA|MINA can't
> > generate inexact, overflow, or underflow FP exceptions
> >
> 
> The "MIPS64® Instruction Set Reference Manual" v6.00 mentions that all
> five FP exception are possible for MAX|MIN|MAXA|MINA, but in v6.05, the
> list was reduced to only two, as you hinted. I am going to sync the commit
> message with v6.05 of the document.
> 
> > ... and in practice
> > the only FPE generated by emulating these instructions is invalid
> > operation for MADDF/MSUBF. So presumably that's the only case we really
> > care about.
> > 
> > I.e. the MADDF/MSUBF invalid operation should be counted, but crucially
> > the setting of rcsr bits allows it to generate a SIGFPE which from a
> > glance it doesn't appear to do until this patch. The other changes are
> > redundant and harmless.
> > 
> > Does that sound correct? (appologies if I'm missing something, I'm just
> > reading the code, and reading FPU emulation code late at night is
> > probably asking for trouble).
> >
> 
> You are close, but not quite, I'll explain that in a moment.
> 
> First, just to note that SIGFPE will be generated if the condition
> 
> ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E)
> 
> is met (the code is almost at the end of fpu_emu(), cp1emu.c, line 1557).
> ctx is one of the arguments of fpu_emu(), but, in the current state of the
> code, by analyzing several levels of invocations, it can be concluded
> that ctx will always be equal to &current->thread.fpu. So, the register
> current->thread.fpu->fcr31 is actually important here.
> 
> Now, let's consider, for simplicity, the case of MADDF operation resulting
> in an overflow caused by addition of two large FP numbers. The "special"
> treatment of such case will be done within invocation of ieee754dp_format(),

Ah yes, obviously an MADDF can generate those other exception bits :-)

> which will in turn (in this particular example) execute
> ieee754_setcx(IEEE754_OVERFLOW), which will further execute
> 
> 	ieee754_csr.cx |= flags;
> 	ieee754_csr.sx |= flags;
> 
> and, since ieee754_csr is macro for &current->thread.fpu.fcr31, this will result
> in setting tworelevant and correct bits in current->thread.fpu->fcr31.
> 
> This means that condition from few paragraphs above will be met, and SIGFPE
> will be generated.

But just before that condition it does:
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;

I.e. it clears the X bits used in the condition, and overrides them
based on rcsr, which is initialised to 0 and is only set after the
copcsr label and in a couple of other cases I don't think we'd be
hitting for MADDF.

Cheers
James

> 
> Whole above scenario happens regardless of inclusion of this patch.
> 
> Actually, setting exception bits within "copcsr label code" seems redundant.
> It though does no harm. I have some theory why is this code here, and why
> we even may want to keep it as is, but this would be too much for this mail.
> 
> > 
> > Given the potential fixing of SIGFPE in that case should this be tagged
> > for stable?
> > 
> 
> As I explained above, SIGFPE behavior is already correct, without this patch.
> This patch fixes only debugfs stats. So, it is not that critical.
> 
> Looking forward to your response.
> 
> Aleksandar

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RE: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[Aleksandar Markovic]

(resending since the previous mail was rejected by the mailing list because of html format)

> Subject: Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions
> Date: Thursday, October 12, 2017 12:17 CEST
> From: James Hogan <james.hogan@mips.com>>
> > ...
> > if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E)
> > ...
>
> But just before that condition it does:
>
> ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
> I.e. it clears the X bits used in the condition, and overrides them,
> based on rcsr, which is initialised to 0 and is only set after the
> copcsr label and in a couple of other cases I don't think we'd be
> hitting for MADDF.
>

The code is odd and deceiving here. Let's see the whole "copcsr label"
code segment:
 
copcsr:
if (ieee754_cxtest(IEEE754_INEXACT)) {
    MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
    rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
}
if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
    MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
    rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
}
if (ieee754_cxtest(IEEE754_OVERFLOW)) {
    MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
    rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
}
if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
    MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
    rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
}
 
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
    /*printk ("SIGFPE: FPU csr = %08x\n",
    ctx->fcr31); */
    return SIGFPE;
}


Value of rcsr will be dictated by series of invocations to ieee754_cxtest(),
which, in fact, means that exception bits will be copied from fcr31 to rcsr.

Then, fcr31 exception bits are cleared and set to the values they had just
before clearing.

Obviously, this will not do anything in our scenarios.

However, the patch is about correct setting of debugfs stats, and this code
segment correctly does this.

May I suggest that we accept my patch as is, and if anybody for any reason
wants to deal further with related code, this should be done in a separate
fix/patch?

Regards,
Aleksandar

Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[James Hogan]

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On Thu, Oct 12, 2017 at 03:57:50PM +0200, Aleksandar Markovic wrote:
> 
> > Subject: Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions
> > Date: Thursday, October 12, 2017 12:17 CEST
> > From: James Hogan <james.hogan@mips.com>>@badag02.ba.imgtec.org>
> > > ...
> > > if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E)
> > > ...
> >
> > But just before that condition it does:
> >
> > ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
> > I.e. it clears the X bits used in the condition, and overrides them,
> > based on rcsr, which is initialised to 0 and is only set after the
> > copcsr label and in a couple of other cases I don't think we'd be
> > hitting for MADDF.
> >
> 
> The code is odd and deceiving here. Let's see the whole "copcsr label"
> code segment: copcsr:if (ieee754_cxtest(IEEE754_INEXACT)) {  MIPS_FPU_EMU_INC_STATS(ieee754_inexact);  rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;}if (ieee754_cxtest(IEEE754_UNDERFLOW)) {  MIPS_FPU_EMU_INC_STATS(ieee754_underflow);  rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;}if (ieee754_cxtest(IEEE754_OVERFLOW)) {  MIPS_FPU_EMU_INC_STATS(ieee754_overflow);  rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;}  if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {  MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);  rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;} ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {  /*printk ("SIGFPE: FPU csr = %08x\n",  ctx->fcr31); */  return SIGFPE;}

Note: thats the one in fpux_emu(), not fpu_emu() which this patch
modifies. In fpu_emu() the copying of bits from rcsr to fcr32 and the
SIGFPE checking takes place outside of the switch, after other stuff can
modify rcsr.

> 
> 
> Value of rcsr will be dictated by series of invocations to ieee754_cxtest(),
> which, in fact, means that exception bits will be copied from fcr31 to rcsr.
> 
> Then, fcr31 exception bits are cleared and set to the values they had just
> before clearing.
> 
> Obviously, this will not do anything in our scenarios.
> 
> However, the patch is about correct setting of debugfs stats, and this code
> segment correctly does this.

Right, but its not going to even get to copcsr until this patch, so the
SIGFPE handling is I think fixed by this patch, i.e. it isn't just about
the stats.

> 
> May I suggest that we accept my patch as is, and if anybody for any reason
> wants to deal further with related code, this should be done in a separate
> fix/patch?

This patch fixes something, I think it should
a) be clear in the commit message what is fixed
b) be tagged for stable (though that can always be done
retrospectively).

Cheers
James

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RE: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[Aleksandar Markovic]

> Right, but its not going to even get to copcsr until this patch, so the
> SIGFPE handling is I think fixed by this patch, i.e. it isn't just about
> the stats.

On more detailed code inspection, you are right.

> This patch fixes something, I think it should
> a) be clear in the commit message what is fixed
> b) be tagged for stable (though that can always be done
> retrospectively)

If you agree, I am going to submit v2 of the series, that would fully
address these concerns.

Additionally, it seems to me that a new round of testing that tests
involved code paths under various scenarios would be appropriate
and I am going to do that.

> Note: thats the one in fpux_emu(), not fpu_emu() which this patch
> modifies.

Yes, my bad, wanting to respond as quickly as possible, I inserted
the segment from fpux_emu(), not fpu_emu() as I should have.

By the way, and not related to this patch, I see only 4 (out of 5)
exceptions are handled in fpux_emu() case (division-by-zero is not
handled), I presume this is fine (probably division-by-zero not
needed), isn't it?

I truly appreciate your analysis and help.

Aleksandar

________________________________________
From: James Hogan [james.hogan@mips.com]
Sent: Thursday, October 12, 2017 7:44 AM
To: Aleksandar Markovic
Cc: Miodrag Dinic; Paul Burton; Petar Jovanovic; Raghu Gandham; Ralf Baechle; Aleksandar Markovic; linux-mips@linux-mips.org; Douglas Leung; Goran Ferenc; linux-kernel@vger.kernel.org; Maciej Rozycki; Manuel Lauss; Masahiro Yamada
Subject: Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

On Thu, Oct 12, 2017 at 03:57:50PM +0200, Aleksandar Markovic wrote:
>
> > Subject: Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions
> > Date: Thursday, October 12, 2017 12:17 CEST
> > From: James Hogan <james.hogan@mips.com>>@badag02.ba.imgtec.org>
> > > ...
> > > if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E)
> > > ...
> >
> > But just before that condition it does:
> >
> > ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
> > I.e. it clears the X bits used in the condition, and overrides them,
> > based on rcsr, which is initialised to 0 and is only set after the
> > copcsr label and in a couple of other cases I don't think we'd be
> > hitting for MADDF.
> >
>
> The code is odd and deceiving here. Let's see the whole "copcsr label"
> code segment: copcsr:if (ieee754_cxtest(IEEE754_INEXACT)) {  MIPS_FPU_EMU_INC_STATS(ieee754_inexact);  rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;}if (ieee754_cxtest(IEEE754_UNDERFLOW)) {  MIPS_FPU_EMU_INC_STATS(ieee754_underflow);  rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;}if (ieee754_cxtest(IEEE754_OVERFLOW)) {  MIPS_FPU_EMU_INC_STATS(ieee754_overflow);  rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;}  if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {  MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);  rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;} ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {  /*printk ("SIGFPE: FPU csr = %08x\n",  ctx->fcr31); */  return SIGFPE;}

Note: thats the one in fpux_emu(), not fpu_emu() which this patch
modifies. In fpu_emu() the copying of bits from rcsr to fcr32 and the
SIGFPE checking takes place outside of the switch, after other stuff can
modify rcsr.

>
>
> Value of rcsr will be dictated by series of invocations to ieee754_cxtest(),
> which, in fact, means that exception bits will be copied from fcr31 to rcsr.
>
> Then, fcr31 exception bits are cleared and set to the values they had just
> before clearing.
>
> Obviously, this will not do anything in our scenarios.
>
> However, the patch is about correct setting of debugfs stats, and this code
> segment correctly does this.



>
> May I suggest that we accept my patch as is, and if anybody for any reason
> wants to deal further with related code, this should be done in a separate
> fix/patch?

This patch fixes something, I think it should
a) be clear in the commit message what is fixed
b) be tagged for stable (though that can always be done
retrospectively).

Cheers
James

Re: [PATCH 1/2] MIPS: math-emu: Update debugfs FP exception stats for certain instructions

[James Hogan]

On Thu, Oct 12, 2017 at 03:54:48PM +0000, Aleksandar Markovic wrote:
> > This patch fixes something, I think it should
> > a) be clear in the commit message what is fixed
> > b) be tagged for stable (though that can always be done
> > retrospectively)
> 
> If you agree, I am going to submit v2 of the series, that would fully
> address these concerns.
> 
> Additionally, it seems to me that a new round of testing that tests
> involved code paths under various scenarios would be appropriate
> and I am going to do that.

awesome, thanks!

> > Note: thats the one in fpux_emu(), not fpu_emu() which this patch
> > modifies.
> 
> Yes, my bad, wanting to respond as quickly as possible, I inserted
> the segment from fpux_emu(), not fpu_emu() as I should have.
> 
> By the way, and not related to this patch, I see only 4 (out of 5)
> exceptions are handled in fpux_emu() case (division-by-zero is not
> handled), I presume this is fine (probably division-by-zero not
> needed), isn't it?

Yeh I just spotted that too.

I agree that it only seems to be division instructions (fdiv_op,
frsqrt_op, and frecip_op) that need it, which are all handled in
fpu_emu(), so it should be fine as is.

> 
> I truly appreciate your analysis and help.

No problem

Cheers
James

[PATCH 2/2] MIPS: math-emu: Use preferred flavor of unsigned integer declarations

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>

Fix occurences of unsigned integer declarations that are not
preferred by standards of checkpatch scripts. This removes
significant number of checkpatch warnings in math-emu
directory (several files will become completely warning-free),
and thus makes easier to spot (now and in the future) other
perhaps more significant checkpatch errors and warnings.

Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
 arch/mips/math-emu/cp1emu.c     | 18 ++++++++++--------
 arch/mips/math-emu/dp_maddf.c   |  8 ++++----
 arch/mips/math-emu/dp_mul.c     |  8 ++++----
 arch/mips/math-emu/dp_sqrt.c    |  4 ++--
 arch/mips/math-emu/ieee754.h    | 15 ++++++++-------
 arch/mips/math-emu/ieee754int.h |  6 +++---
 arch/mips/math-emu/ieee754sp.c  |  4 ++--
 arch/mips/math-emu/ieee754sp.h  |  2 +-
 arch/mips/math-emu/sp_div.c     |  4 ++--
 arch/mips/math-emu/sp_fint.c    |  2 +-
 arch/mips/math-emu/sp_maddf.c   |  6 +++---
 arch/mips/math-emu/sp_mul.c     | 10 +++++-----
 12 files changed, 45 insertions(+), 42 deletions(-)

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index d2fcb30..9f145e1 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -810,7 +810,7 @@ do {									\
 #define SITOREG(si, x)							\
 do {									\
 	if (cop1_64bit(xcp) && !hybrid_fprs()) {			\
-		unsigned i;						\
+		unsigned int i;						\
 		set_fpr32(&ctx->fpr[x], 0, si);				\
 		for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)	\
 			set_fpr32(&ctx->fpr[x], i, 0);			\
@@ -823,7 +823,7 @@ do {									\
 
 #define SITOHREG(si, x)							\
 do {									\
-	unsigned i;							\
+	unsigned int i;							\
 	set_fpr32(&ctx->fpr[x], 1, si);					\
 	for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)		\
 		set_fpr32(&ctx->fpr[x], i, 0);				\
@@ -834,7 +834,7 @@ do {									\
 
 #define DITOREG(di, x)							\
 do {									\
-	unsigned fpr, i;						\
+	unsigned int fpr, i;						\
 	fpr = (x) & ~(cop1_64bit(xcp) ^ 1);				\
 	set_fpr64(&ctx->fpr[fpr], 0, di);				\
 	for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)		\
@@ -1465,7 +1465,7 @@ DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 	mips_instruction ir, void __user **fault_addr)
 {
-	unsigned rcsr = 0;	/* resulting csr */
+	unsigned int rcsr = 0;	/* resulting csr */
 
 	MIPS_FPU_EMU_INC_STATS(cp1xops);
 
@@ -1661,10 +1661,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 	mips_instruction ir)
 {
 	int rfmt;		/* resulting format */
-	unsigned rcsr = 0;	/* resulting csr */
+	unsigned int rcsr = 0;	/* resulting csr */
 	unsigned int oldrm;
 	unsigned int cbit;
-	unsigned cond;
+	unsigned int cond;
 	union {
 		union ieee754dp d;
 		union ieee754sp s;
@@ -2029,9 +2029,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 
 		default:
 			if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
-				unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
+				unsigned int cmpop;
 				union ieee754sp fs, ft;
 
+				cmpop = MIPSInst_FUNC(ir) - fcmp_op;
 				SPFROMREG(fs, MIPSInst_FS(ir));
 				SPFROMREG(ft, MIPSInst_FT(ir));
 				rv.w = ieee754sp_cmp(fs, ft,
@@ -2379,9 +2380,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 
 		default:
 			if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
-				unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
+				unsigned int cmpop;
 				union ieee754dp fs, ft;
 
+				cmpop = MIPSInst_FUNC(ir) - fcmp_op;
 				DPFROMREG(fs, MIPSInst_FS(ir));
 				DPFROMREG(ft, MIPSInst_FT(ir));
 				rv.w = ieee754dp_cmp(fs, ft,
diff --git a/arch/mips/math-emu/dp_maddf.c b/arch/mips/math-emu/dp_maddf.c
index e0d9be5..7ad79ed 100644
--- a/arch/mips/math-emu/dp_maddf.c
+++ b/arch/mips/math-emu/dp_maddf.c
@@ -45,10 +45,10 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
 {
 	int re;
 	int rs;
-	unsigned lxm;
-	unsigned hxm;
-	unsigned lym;
-	unsigned hym;
+	unsigned int lxm;
+	unsigned int hxm;
+	unsigned int lym;
+	unsigned int hym;
 	u64 lrm;
 	u64 hrm;
 	u64 lzm;
diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
index 87d0b44..60c8bfe 100644
--- a/arch/mips/math-emu/dp_mul.c
+++ b/arch/mips/math-emu/dp_mul.c
@@ -26,10 +26,10 @@ union ieee754dp ieee754dp_mul(union ieee754dp x, union ieee754dp y)
 	int re;
 	int rs;
 	u64 rm;
-	unsigned lxm;
-	unsigned hxm;
-	unsigned lym;
-	unsigned hym;
+	unsigned int lxm;
+	unsigned int hxm;
+	unsigned int lym;
+	unsigned int hym;
 	u64 lrm;
 	u64 hrm;
 	u64 t;
diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c
index cd5bc08..cea907b 100644
--- a/arch/mips/math-emu/dp_sqrt.c
+++ b/arch/mips/math-emu/dp_sqrt.c
@@ -21,7 +21,7 @@
 
 #include "ieee754dp.h"
 
-static const unsigned table[] = {
+static const unsigned int table[] = {
 	0, 1204, 3062, 5746, 9193, 13348, 18162, 23592,
 	29598, 36145, 43202, 50740, 58733, 67158, 75992,
 	85215, 83599, 71378, 60428, 50647, 41945, 34246,
@@ -33,7 +33,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
 {
 	struct _ieee754_csr oldcsr;
 	union ieee754dp y, z, t;
-	unsigned scalx, yh;
+	unsigned int scalx, yh;
 	COMPXDP;
 
 	EXPLODEXDP;
diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
index 92dc8fa..e0eb7a9 100644
--- a/arch/mips/math-emu/ieee754.h
+++ b/arch/mips/math-emu/ieee754.h
@@ -165,11 +165,12 @@ struct _ieee754_csr {
 };
 #define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
 
-static inline unsigned ieee754_getrm(void)
+static inline unsigned int ieee754_getrm(void)
 {
 	return (ieee754_csr.rm);
 }
-static inline unsigned ieee754_setrm(unsigned rm)
+
+static inline unsigned int ieee754_setrm(unsigned int rm)
 {
 	return (ieee754_csr.rm = rm);
 }
@@ -177,14 +178,14 @@ static inline unsigned ieee754_setrm(unsigned rm)
 /*
  * get current exceptions
  */
-static inline unsigned ieee754_getcx(void)
+static inline unsigned int ieee754_getcx(void)
 {
 	return (ieee754_csr.cx);
 }
 
 /* test for current exception condition
  */
-static inline int ieee754_cxtest(unsigned n)
+static inline int ieee754_cxtest(unsigned int n)
 {
 	return (ieee754_csr.cx & n);
 }
@@ -192,21 +193,21 @@ static inline int ieee754_cxtest(unsigned n)
 /*
  * get sticky exceptions
  */
-static inline unsigned ieee754_getsx(void)
+static inline unsigned int ieee754_getsx(void)
 {
 	return (ieee754_csr.sx);
 }
 
 /* clear sticky conditions
 */
-static inline unsigned ieee754_clrsx(void)
+static inline unsigned int ieee754_clrsx(void)
 {
 	return (ieee754_csr.sx = 0);
 }
 
 /* test for sticky exception condition
  */
-static inline int ieee754_sxtest(unsigned n)
+static inline int ieee754_sxtest(unsigned int n)
 {
 	return (ieee754_csr.sx & n);
 }
diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index dd2071f..06ac0e2 100644
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -54,13 +54,13 @@ static inline int ieee754_class_nan(int xc)
 }
 
 #define COMPXSP \
-	unsigned xm; int xe; int xs __maybe_unused; int xc
+	unsigned int xm; int xe; int xs __maybe_unused; int xc
 
 #define COMPYSP \
-	unsigned ym; int ye; int ys; int yc
+	unsigned int ym; int ye; int ys; int yc
 
 #define COMPZSP \
-	unsigned zm; int ze; int zs; int zc
+	unsigned int zm; int ze; int zs; int zc
 
 #define EXPLODESP(v, vc, vs, ve, vm)					\
 {									\
diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
index 260e6896..8423e4c 100644
--- a/arch/mips/math-emu/ieee754sp.c
+++ b/arch/mips/math-emu/ieee754sp.c
@@ -65,7 +65,7 @@ union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
 	return r;
 }
 
-static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
+static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm)
 {
 	/* inexact must round of 3 bits
 	 */
@@ -96,7 +96,7 @@ static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
  * xe is an unbiased exponent
  * xm is 3bit extended precision value.
  */
-union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
+union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm)
 {
 	assert(xm);		/* we don't gen exact zeros (probably should) */
 
diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
index 0f63e42..8c5a638 100644
--- a/arch/mips/math-emu/ieee754sp.h
+++ b/arch/mips/math-emu/ieee754sp.h
@@ -69,7 +69,7 @@ static inline int ieee754sp_finite(union ieee754sp x)
 #define SPDNORMY	SPDNORMx(ym, ye)
 #define SPDNORMZ	SPDNORMx(zm, ze)
 
-static inline union ieee754sp buildsp(int s, int bx, unsigned m)
+static inline union ieee754sp buildsp(int s, int bx, unsigned int m)
 {
 	union ieee754sp r;
 
diff --git a/arch/mips/math-emu/sp_div.c b/arch/mips/math-emu/sp_div.c
index 27f6db3..23587b3 100644
--- a/arch/mips/math-emu/sp_div.c
+++ b/arch/mips/math-emu/sp_div.c
@@ -23,9 +23,9 @@
 
 union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y)
 {
-	unsigned rm;
+	unsigned int rm;
 	int re;
-	unsigned bm;
+	unsigned int bm;
 
 	COMPXSP;
 	COMPYSP;
diff --git a/arch/mips/math-emu/sp_fint.c b/arch/mips/math-emu/sp_fint.c
index d5d8495..1a35d12 100644
--- a/arch/mips/math-emu/sp_fint.c
+++ b/arch/mips/math-emu/sp_fint.c
@@ -23,7 +23,7 @@
 
 union ieee754sp ieee754sp_fint(int x)
 {
-	unsigned xm;
+	unsigned int xm;
 	int xe;
 	int xs;
 
diff --git a/arch/mips/math-emu/sp_maddf.c b/arch/mips/math-emu/sp_maddf.c
index 7195fe7..f823338 100644
--- a/arch/mips/math-emu/sp_maddf.c
+++ b/arch/mips/math-emu/sp_maddf.c
@@ -20,9 +20,9 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
 {
 	int re;
 	int rs;
-	unsigned rm;
-	uint64_t rm64;
-	uint64_t zm64;
+	unsigned int rm;
+	u64 rm64;
+	u64 zm64;
 	int s;
 
 	COMPXSP;
diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c
index d910c43..4015101 100644
--- a/arch/mips/math-emu/sp_mul.c
+++ b/arch/mips/math-emu/sp_mul.c
@@ -25,15 +25,15 @@ union ieee754sp ieee754sp_mul(union ieee754sp x, union ieee754sp y)
 {
 	int re;
 	int rs;
-	unsigned rm;
+	unsigned int rm;
 	unsigned short lxm;
 	unsigned short hxm;
 	unsigned short lym;
 	unsigned short hym;
-	unsigned lrm;
-	unsigned hrm;
-	unsigned t;
-	unsigned at;
+	unsigned int lrm;
+	unsigned int hrm;
+	unsigned int t;
+	unsigned int at;
 
 	COMPXSP;
 	COMPYSP;
-- 
2.7.4

Re: [PATCH 2/2] MIPS: math-emu: Use preferred flavor of unsigned integer declarations

[James Hogan]

On Fri, Oct 06, 2017 at 07:29:01PM +0200, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> 
> Fix occurences of unsigned integer declarations that are not
> preferred by standards of checkpatch scripts. This removes
> significant number of checkpatch warnings in math-emu
> directory (several files will become completely warning-free),
> and thus makes easier to spot (now and in the future) other
> perhaps more significant checkpatch errors and warnings.
> 
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>

Reviewed-by: James Hogan <jhogan@kernel.org>

Cheers
James

> ---
>  arch/mips/math-emu/cp1emu.c     | 18 ++++++++++--------
>  arch/mips/math-emu/dp_maddf.c   |  8 ++++----
>  arch/mips/math-emu/dp_mul.c     |  8 ++++----
>  arch/mips/math-emu/dp_sqrt.c    |  4 ++--
>  arch/mips/math-emu/ieee754.h    | 15 ++++++++-------
>  arch/mips/math-emu/ieee754int.h |  6 +++---
>  arch/mips/math-emu/ieee754sp.c  |  4 ++--
>  arch/mips/math-emu/ieee754sp.h  |  2 +-
>  arch/mips/math-emu/sp_div.c     |  4 ++--
>  arch/mips/math-emu/sp_fint.c    |  2 +-
>  arch/mips/math-emu/sp_maddf.c   |  6 +++---
>  arch/mips/math-emu/sp_mul.c     | 10 +++++-----
>  12 files changed, 45 insertions(+), 42 deletions(-)
> 
> diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
> index d2fcb30..9f145e1 100644
> --- a/arch/mips/math-emu/cp1emu.c
> +++ b/arch/mips/math-emu/cp1emu.c
> @@ -810,7 +810,7 @@ do {									\
>  #define SITOREG(si, x)							\
>  do {									\
>  	if (cop1_64bit(xcp) && !hybrid_fprs()) {			\
> -		unsigned i;						\
> +		unsigned int i;						\
>  		set_fpr32(&ctx->fpr[x], 0, si);				\
>  		for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)	\
>  			set_fpr32(&ctx->fpr[x], i, 0);			\
> @@ -823,7 +823,7 @@ do {									\
>  
>  #define SITOHREG(si, x)							\
>  do {									\
> -	unsigned i;							\
> +	unsigned int i;							\
>  	set_fpr32(&ctx->fpr[x], 1, si);					\
>  	for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)		\
>  		set_fpr32(&ctx->fpr[x], i, 0);				\
> @@ -834,7 +834,7 @@ do {									\
>  
>  #define DITOREG(di, x)							\
>  do {									\
> -	unsigned fpr, i;						\
> +	unsigned int fpr, i;						\
>  	fpr = (x) & ~(cop1_64bit(xcp) ^ 1);				\
>  	set_fpr64(&ctx->fpr[fpr], 0, di);				\
>  	for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)		\
> @@ -1465,7 +1465,7 @@ DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
>  static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  	mips_instruction ir, void __user **fault_addr)
>  {
> -	unsigned rcsr = 0;	/* resulting csr */
> +	unsigned int rcsr = 0;	/* resulting csr */
>  
>  	MIPS_FPU_EMU_INC_STATS(cp1xops);
>  
> @@ -1661,10 +1661,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  	mips_instruction ir)
>  {
>  	int rfmt;		/* resulting format */
> -	unsigned rcsr = 0;	/* resulting csr */
> +	unsigned int rcsr = 0;	/* resulting csr */
>  	unsigned int oldrm;
>  	unsigned int cbit;
> -	unsigned cond;
> +	unsigned int cond;
>  	union {
>  		union ieee754dp d;
>  		union ieee754sp s;
> @@ -2029,9 +2029,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  
>  		default:
>  			if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
> -				unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
> +				unsigned int cmpop;
>  				union ieee754sp fs, ft;
>  
> +				cmpop = MIPSInst_FUNC(ir) - fcmp_op;
>  				SPFROMREG(fs, MIPSInst_FS(ir));
>  				SPFROMREG(ft, MIPSInst_FT(ir));
>  				rv.w = ieee754sp_cmp(fs, ft,
> @@ -2379,9 +2380,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
>  
>  		default:
>  			if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
> -				unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
> +				unsigned int cmpop;
>  				union ieee754dp fs, ft;
>  
> +				cmpop = MIPSInst_FUNC(ir) - fcmp_op;
>  				DPFROMREG(fs, MIPSInst_FS(ir));
>  				DPFROMREG(ft, MIPSInst_FT(ir));
>  				rv.w = ieee754dp_cmp(fs, ft,
> diff --git a/arch/mips/math-emu/dp_maddf.c b/arch/mips/math-emu/dp_maddf.c
> index e0d9be5..7ad79ed 100644
> --- a/arch/mips/math-emu/dp_maddf.c
> +++ b/arch/mips/math-emu/dp_maddf.c
> @@ -45,10 +45,10 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
>  {
>  	int re;
>  	int rs;
> -	unsigned lxm;
> -	unsigned hxm;
> -	unsigned lym;
> -	unsigned hym;
> +	unsigned int lxm;
> +	unsigned int hxm;
> +	unsigned int lym;
> +	unsigned int hym;
>  	u64 lrm;
>  	u64 hrm;
>  	u64 lzm;
> diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
> index 87d0b44..60c8bfe 100644
> --- a/arch/mips/math-emu/dp_mul.c
> +++ b/arch/mips/math-emu/dp_mul.c
> @@ -26,10 +26,10 @@ union ieee754dp ieee754dp_mul(union ieee754dp x, union ieee754dp y)
>  	int re;
>  	int rs;
>  	u64 rm;
> -	unsigned lxm;
> -	unsigned hxm;
> -	unsigned lym;
> -	unsigned hym;
> +	unsigned int lxm;
> +	unsigned int hxm;
> +	unsigned int lym;
> +	unsigned int hym;
>  	u64 lrm;
>  	u64 hrm;
>  	u64 t;
> diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c
> index cd5bc08..cea907b 100644
> --- a/arch/mips/math-emu/dp_sqrt.c
> +++ b/arch/mips/math-emu/dp_sqrt.c
> @@ -21,7 +21,7 @@
>  
>  #include "ieee754dp.h"
>  
> -static const unsigned table[] = {
> +static const unsigned int table[] = {
>  	0, 1204, 3062, 5746, 9193, 13348, 18162, 23592,
>  	29598, 36145, 43202, 50740, 58733, 67158, 75992,
>  	85215, 83599, 71378, 60428, 50647, 41945, 34246,
> @@ -33,7 +33,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
>  {
>  	struct _ieee754_csr oldcsr;
>  	union ieee754dp y, z, t;
> -	unsigned scalx, yh;
> +	unsigned int scalx, yh;
>  	COMPXDP;
>  
>  	EXPLODEXDP;
> diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
> index 92dc8fa..e0eb7a9 100644
> --- a/arch/mips/math-emu/ieee754.h
> +++ b/arch/mips/math-emu/ieee754.h
> @@ -165,11 +165,12 @@ struct _ieee754_csr {
>  };
>  #define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
>  
> -static inline unsigned ieee754_getrm(void)
> +static inline unsigned int ieee754_getrm(void)
>  {
>  	return (ieee754_csr.rm);
>  }
> -static inline unsigned ieee754_setrm(unsigned rm)
> +
> +static inline unsigned int ieee754_setrm(unsigned int rm)
>  {
>  	return (ieee754_csr.rm = rm);
>  }
> @@ -177,14 +178,14 @@ static inline unsigned ieee754_setrm(unsigned rm)
>  /*
>   * get current exceptions
>   */
> -static inline unsigned ieee754_getcx(void)
> +static inline unsigned int ieee754_getcx(void)
>  {
>  	return (ieee754_csr.cx);
>  }
>  
>  /* test for current exception condition
>   */
> -static inline int ieee754_cxtest(unsigned n)
> +static inline int ieee754_cxtest(unsigned int n)
>  {
>  	return (ieee754_csr.cx & n);
>  }
> @@ -192,21 +193,21 @@ static inline int ieee754_cxtest(unsigned n)
>  /*
>   * get sticky exceptions
>   */
> -static inline unsigned ieee754_getsx(void)
> +static inline unsigned int ieee754_getsx(void)
>  {
>  	return (ieee754_csr.sx);
>  }
>  
>  /* clear sticky conditions
>  */
> -static inline unsigned ieee754_clrsx(void)
> +static inline unsigned int ieee754_clrsx(void)
>  {
>  	return (ieee754_csr.sx = 0);
>  }
>  
>  /* test for sticky exception condition
>   */
> -static inline int ieee754_sxtest(unsigned n)
> +static inline int ieee754_sxtest(unsigned int n)
>  {
>  	return (ieee754_csr.sx & n);
>  }
> diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
> index dd2071f..06ac0e2 100644
> --- a/arch/mips/math-emu/ieee754int.h
> +++ b/arch/mips/math-emu/ieee754int.h
> @@ -54,13 +54,13 @@ static inline int ieee754_class_nan(int xc)
>  }
>  
>  #define COMPXSP \
> -	unsigned xm; int xe; int xs __maybe_unused; int xc
> +	unsigned int xm; int xe; int xs __maybe_unused; int xc
>  
>  #define COMPYSP \
> -	unsigned ym; int ye; int ys; int yc
> +	unsigned int ym; int ye; int ys; int yc
>  
>  #define COMPZSP \
> -	unsigned zm; int ze; int zs; int zc
> +	unsigned int zm; int ze; int zs; int zc
>  
>  #define EXPLODESP(v, vc, vs, ve, vm)					\
>  {									\
> diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
> index 260e6896..8423e4c 100644
> --- a/arch/mips/math-emu/ieee754sp.c
> +++ b/arch/mips/math-emu/ieee754sp.c
> @@ -65,7 +65,7 @@ union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
>  	return r;
>  }
>  
> -static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
> +static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm)
>  {
>  	/* inexact must round of 3 bits
>  	 */
> @@ -96,7 +96,7 @@ static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
>   * xe is an unbiased exponent
>   * xm is 3bit extended precision value.
>   */
> -union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
> +union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm)
>  {
>  	assert(xm);		/* we don't gen exact zeros (probably should) */
>  
> diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
> index 0f63e42..8c5a638 100644
> --- a/arch/mips/math-emu/ieee754sp.h
> +++ b/arch/mips/math-emu/ieee754sp.h
> @@ -69,7 +69,7 @@ static inline int ieee754sp_finite(union ieee754sp x)
>  #define SPDNORMY	SPDNORMx(ym, ye)
>  #define SPDNORMZ	SPDNORMx(zm, ze)
>  
> -static inline union ieee754sp buildsp(int s, int bx, unsigned m)
> +static inline union ieee754sp buildsp(int s, int bx, unsigned int m)
>  {
>  	union ieee754sp r;
>  
> diff --git a/arch/mips/math-emu/sp_div.c b/arch/mips/math-emu/sp_div.c
> index 27f6db3..23587b3 100644
> --- a/arch/mips/math-emu/sp_div.c
> +++ b/arch/mips/math-emu/sp_div.c
> @@ -23,9 +23,9 @@
>  
>  union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y)
>  {
> -	unsigned rm;
> +	unsigned int rm;
>  	int re;
> -	unsigned bm;
> +	unsigned int bm;
>  
>  	COMPXSP;
>  	COMPYSP;
> diff --git a/arch/mips/math-emu/sp_fint.c b/arch/mips/math-emu/sp_fint.c
> index d5d8495..1a35d12 100644
> --- a/arch/mips/math-emu/sp_fint.c
> +++ b/arch/mips/math-emu/sp_fint.c
> @@ -23,7 +23,7 @@
>  
>  union ieee754sp ieee754sp_fint(int x)
>  {
> -	unsigned xm;
> +	unsigned int xm;
>  	int xe;
>  	int xs;
>  
> diff --git a/arch/mips/math-emu/sp_maddf.c b/arch/mips/math-emu/sp_maddf.c
> index 7195fe7..f823338 100644
> --- a/arch/mips/math-emu/sp_maddf.c
> +++ b/arch/mips/math-emu/sp_maddf.c
> @@ -20,9 +20,9 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
>  {
>  	int re;
>  	int rs;
> -	unsigned rm;
> -	uint64_t rm64;
> -	uint64_t zm64;
> +	unsigned int rm;
> +	u64 rm64;
> +	u64 zm64;
>  	int s;
>  
>  	COMPXSP;
> diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c
> index d910c43..4015101 100644
> --- a/arch/mips/math-emu/sp_mul.c
> +++ b/arch/mips/math-emu/sp_mul.c
> @@ -25,15 +25,15 @@ union ieee754sp ieee754sp_mul(union ieee754sp x, union ieee754sp y)
>  {
>  	int re;
>  	int rs;
> -	unsigned rm;
> +	unsigned int rm;
>  	unsigned short lxm;
>  	unsigned short hxm;
>  	unsigned short lym;
>  	unsigned short hym;
> -	unsigned lrm;
> -	unsigned hrm;
> -	unsigned t;
> -	unsigned at;
> +	unsigned int lrm;
> +	unsigned int hrm;
> +	unsigned int t;
> +	unsigned int at;
>  
>  	COMPXSP;
>  	COMPYSP;
> -- 
> 2.7.4
>