From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756075AbdJJKQv (ORCPT ); Tue, 10 Oct 2017 06:16:51 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:32510 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755871AbdJJKQW (ORCPT ); Tue, 10 Oct 2017 06:16:22 -0400 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 2/4] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Date: Tue, 10 Oct 2017 15:46:04 +0530 Message-ID: <20171010101606.15951-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 82cb875e4cec..455cb74a475c 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,10 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the + register offset to specify 1 lane or 2 lane. + - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the + register offset to specify lane selection. HOST MODE ========= -- 2.11.0